static_inst.hh (8541:27aaee8ec7cc) static_inst.hh (8542:7230ff0738e3)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36
37#include "arch/registers.hh"
38#include "arch/types.hh"
39#include "base/misc.hh"
40#include "base/refcnt.hh"
41#include "base/types.hh"
42#include "config/the_isa.hh"
43#include "cpu/op_class.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36
37#include "arch/registers.hh"
38#include "arch/types.hh"
39#include "base/misc.hh"
40#include "base/refcnt.hh"
41#include "base/types.hh"
42#include "config/the_isa.hh"
43#include "cpu/op_class.hh"
44#include "cpu/static_inst_fwd.hh"
44#include "sim/fault_fwd.hh"
45
46// forward declarations
47struct AlphaSimpleImpl;
48struct OzoneImpl;
49struct SimpleImpl;
50class ThreadContext;
51class DynInst;

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71/**
72 * Base, ISA-independent static instruction class.
73 *
74 * The main component of this class is the vector of flags and the
75 * associated methods for reading them. Any object that can rely
76 * solely on these flags can process instructions without being
77 * recompiled for multiple ISAs.
78 */
45#include "sim/fault_fwd.hh"
46
47// forward declarations
48struct AlphaSimpleImpl;
49struct OzoneImpl;
50struct SimpleImpl;
51class ThreadContext;
52class DynInst;

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72/**
73 * Base, ISA-independent static instruction class.
74 *
75 * The main component of this class is the vector of flags and the
76 * associated methods for reading them. Any object that can rely
77 * solely on these flags can process instructions without being
78 * recompiled for multiple ISAs.
79 */
79class StaticInstBase : public RefCounted
80class StaticInst : public RefCounted
80{
81 public:
81{
82 public:
83 /// Binary extended machine instruction type.
84 typedef TheISA::ExtMachInst ExtMachInst;
85 /// Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
82
87
88 enum {
89 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
90 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
91 };
92
83 /// Set of boolean static instruction properties.
84 ///
85 /// Notes:
86 /// - The IsInteger and IsFloating flags are based on the class of
87 /// registers accessed by the instruction. Although most
88 /// instructions will have exactly one of these two flags set, it
89 /// is possible for an instruction to have neither (e.g., direct
90 /// unconditional branches, memory barriers) or both (e.g., an

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174
175 /// The following are used to track physical register usage
176 /// for machines with separate int & FP reg files.
177 //@{
178 int8_t _numFPDestRegs;
179 int8_t _numIntDestRegs;
180 //@}
181
93 /// Set of boolean static instruction properties.
94 ///
95 /// Notes:
96 /// - The IsInteger and IsFloating flags are based on the class of
97 /// registers accessed by the instruction. Although most
98 /// instructions will have exactly one of these two flags set, it
99 /// is possible for an instruction to have neither (e.g., direct
100 /// unconditional branches, memory barriers) or both (e.g., an

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184
185 /// The following are used to track physical register usage
186 /// for machines with separate int & FP reg files.
187 //@{
188 int8_t _numFPDestRegs;
189 int8_t _numIntDestRegs;
190 //@}
191
182 /// Constructor.
183 /// It's important to initialize everything here to a sane
184 /// default, since the decoder generally only overrides
185 /// the fields that are meaningful for the particular
186 /// instruction.
187 StaticInstBase(OpClass __opClass)
188 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
189 _numFPDestRegs(0), _numIntDestRegs(0)
190 {
191 }
192
193 public:
194
195 /// @name Register information.
196 /// The sum of numFPDestRegs() and numIntDestRegs() equals
197 /// numDestRegs(). The former two functions are used to track
198 /// physical register usage for machines with separate int & FP
199 /// reg files.
200 //@{

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205 /// Number of floating-point destination regs.
206 int8_t numFPDestRegs() const { return _numFPDestRegs; }
207 /// Number of integer destination regs.
208 int8_t numIntDestRegs() const { return _numIntDestRegs; }
209 //@}
210
211 /// @name Flag accessors.
212 /// These functions are used to access the values of the various
192 public:
193
194 /// @name Register information.
195 /// The sum of numFPDestRegs() and numIntDestRegs() equals
196 /// numDestRegs(). The former two functions are used to track
197 /// physical register usage for machines with separate int & FP
198 /// reg files.
199 //@{

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204 /// Number of floating-point destination regs.
205 int8_t numFPDestRegs() const { return _numFPDestRegs; }
206 /// Number of integer destination regs.
207 int8_t numIntDestRegs() const { return _numIntDestRegs; }
208 //@}
209
210 /// @name Flag accessors.
211 /// These functions are used to access the values of the various
213 /// instruction property flags. See StaticInstBase::Flags for descriptions
212 /// instruction property flags. See StaticInst::Flags for descriptions
214 /// of the individual flags.
215 //@{
216
217 bool isNop() const { return flags[IsNop]; }
218
219 bool isMemRef() const { return flags[IsMemRef]; }
220 bool isLoad() const { return flags[IsLoad]; }
221 bool isStore() const { return flags[IsStore]; }

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261 //@}
262
263 void setLastMicroop() { flags[IsLastMicroop] = true; }
264 void setDelayedCommit() { flags[IsDelayedCommit] = true; }
265 void setFlag(Flags f) { flags[f] = true; }
266
267 /// Operation class. Used to select appropriate function unit in issue.
268 OpClass opClass() const { return _opClass; }
213 /// of the individual flags.
214 //@{
215
216 bool isNop() const { return flags[IsNop]; }
217
218 bool isMemRef() const { return flags[IsMemRef]; }
219 bool isLoad() const { return flags[IsLoad]; }
220 bool isStore() const { return flags[IsStore]; }

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260 //@}
261
262 void setLastMicroop() { flags[IsLastMicroop] = true; }
263 void setDelayedCommit() { flags[IsDelayedCommit] = true; }
264 void setFlag(Flags f) { flags[f] = true; }
265
266 /// Operation class. Used to select appropriate function unit in issue.
267 OpClass opClass() const { return _opClass; }
269};
270
271
268
269
272// forward declaration
273class StaticInstPtr;
274
275/**
276 * Generic yet ISA-dependent static instruction class.
277 *
278 * This class builds on StaticInstBase, defining fields and interfaces
279 * that are generic across all ISAs but that differ in details
280 * according to the specific ISA being used.
281 */
282class StaticInst : public StaticInstBase
283{
284 public:
285 /// Binary extended machine instruction type.
286 typedef TheISA::ExtMachInst ExtMachInst;
287 /// Logical register index type.
288 typedef TheISA::RegIndex RegIndex;
289
290 enum {
291 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
292 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
293 };
294
295
296 /// Return logical index (architectural reg num) of i'th destination reg.
297 /// Only the entries from 0 through numDestRegs()-1 are valid.
298 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
299
300 /// Return logical index (architectural reg num) of i'th source reg.
301 /// Only the entries from 0 through numSrcRegs()-1 are valid.
302 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
303

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350
351 /**
352 * Internal function to generate disassembly string.
353 */
354 virtual std::string
355 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
356
357 /// Constructor.
270 /// Return logical index (architectural reg num) of i'th destination reg.
271 /// Only the entries from 0 through numDestRegs()-1 are valid.
272 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
273
274 /// Return logical index (architectural reg num) of i'th source reg.
275 /// Only the entries from 0 through numSrcRegs()-1 are valid.
276 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
277

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324
325 /**
326 * Internal function to generate disassembly string.
327 */
328 virtual std::string
329 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
330
331 /// Constructor.
332 /// It's important to initialize everything here to a sane
333 /// default, since the decoder generally only overrides
334 /// the fields that are meaningful for the particular
335 /// instruction.
358 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
336 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
359 : StaticInstBase(__opClass),
337 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
338 _numFPDestRegs(0), _numIntDestRegs(0),
360 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
361 { }
362
363 public:
364 virtual ~StaticInst();
365
366/**
367 * The execute() signatures are auto-generated by scons based on the

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409 */
410 virtual const std::string &disassemble(Addr pc,
411 const SymbolTable *symtab = 0) const;
412
413 /// Return name of machine instruction
414 std::string getName() { return mnemonic; }
415};
416
339 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
340 { }
341
342 public:
343 virtual ~StaticInst();
344
345/**
346 * The execute() signatures are auto-generated by scons based on the

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388 */
389 virtual const std::string &disassemble(Addr pc,
390 const SymbolTable *symtab = 0) const;
391
392 /// Return name of machine instruction
393 std::string getName() { return mnemonic; }
394};
395
417typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
418
419/// Reference-counted pointer to a StaticInst object.
420/// This type should be used instead of "StaticInst *" so that
421/// StaticInst objects can be properly reference-counted.
422class StaticInstPtr : public RefCountingPtr<StaticInst>
423{
424 public:
425 /// Constructor.
426 StaticInstPtr()
427 : RefCountingPtr<StaticInst>()
428 {
429 }
430
431 /// Conversion from "StaticInst *".
432 StaticInstPtr(StaticInst *p)
433 : RefCountingPtr<StaticInst>(p)
434 {
435 }
436
437 /// Copy constructor.
438 StaticInstPtr(const StaticInstPtr &r)
439 : RefCountingPtr<StaticInst>(r)
440 {
441 }
442
443 /// Convert to pointer to StaticInstBase class.
444 operator const StaticInstBasePtr()
445 {
446 return this->get();
447 }
448};
449
450#endif // __CPU_STATIC_INST_HH__
396#endif // __CPU_STATIC_INST_HH__