static_inst.hh (7680:f4eda002333b) static_inst.hh (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "arch/types.hh"
38#include "arch/registers.hh"
39#include "config/the_isa.hh"
40#include "base/hashmap.hh"
41#include "base/misc.hh"
42#include "base/refcnt.hh"
43#include "base/types.hh"
44#include "cpu/op_class.hh"
45#include "sim/fault.hh"

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65class InorderCPU;
66class SymbolTable;
67class AddrDecodePage;
68
69namespace Trace {
70 class InstRecord;
71}
72
39#include "arch/registers.hh"
40#include "config/the_isa.hh"
41#include "base/hashmap.hh"
42#include "base/misc.hh"
43#include "base/refcnt.hh"
44#include "base/types.hh"
45#include "cpu/op_class.hh"
46#include "sim/fault.hh"

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66class InorderCPU;
67class SymbolTable;
68class AddrDecodePage;
69
70namespace Trace {
71 class InstRecord;
72}
73
73typedef uint16_t MicroPC;
74
75static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1);
76
77static inline MicroPC
78romMicroPC(MicroPC upc)
79{
80 return upc | MicroPCRomBit;
81}
82
83static inline MicroPC
84normalMicroPC(MicroPC upc)
85{
86 return upc & ~MicroPCRomBit;
87}
88
89static inline bool
90isRomMicroPC(MicroPC upc)
91{
92 return MicroPCRomBit & upc;
93}
94
95/**
96 * Base, ISA-independent static instruction class.
97 *
98 * The main component of this class is the vector of flags and the
99 * associated methods for reading them. Any object that can rely
100 * solely on these flags can process instructions without being
101 * recompiled for multiple ISAs.
102 */

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387 virtual ~StaticInst();
388
389/**
390 * The execute() signatures are auto-generated by scons based on the
391 * set of CPU models we are compiling in today.
392 */
393#include "cpu/static_inst_exec_sigs.hh"
394
74/**
75 * Base, ISA-independent static instruction class.
76 *
77 * The main component of this class is the vector of flags and the
78 * associated methods for reading them. Any object that can rely
79 * solely on these flags can process instructions without being
80 * recompiled for multiple ISAs.
81 */

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366 virtual ~StaticInst();
367
368/**
369 * The execute() signatures are auto-generated by scons based on the
370 * set of CPU models we are compiling in today.
371 */
372#include "cpu/static_inst_exec_sigs.hh"
373
374 virtual void advancePC(TheISA::PCState &pcState) const = 0;
375
395 /**
396 * Return the microop that goes with a particular micropc. This should
397 * only be defined/used in macroops which will contain microops
398 */
376 /**
377 * Return the microop that goes with a particular micropc. This should
378 * only be defined/used in macroops which will contain microops
379 */
399 virtual StaticInstPtr fetchMicroop(MicroPC micropc);
380 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
400
401 /**
402 * Return the target address for a PC-relative branch.
403 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
404 * should be true).
405 */
381
382 /**
383 * Return the target address for a PC-relative branch.
384 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
385 * should be true).
386 */
406 virtual Addr branchTarget(Addr branchPC) const;
387 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
407
408 /**
409 * Return the target address for an indirect branch (jump). The
410 * register value is read from the supplied thread context, so
411 * the result is valid only if the thread context is about to
412 * execute the branch in question. Invalid if not an indirect
413 * branch (i.e. isIndirectCtrl() should be true).
414 */
388
389 /**
390 * Return the target address for an indirect branch (jump). The
391 * register value is read from the supplied thread context, so
392 * the result is valid only if the thread context is about to
393 * execute the branch in question. Invalid if not an indirect
394 * branch (i.e. isIndirectCtrl() should be true).
395 */
415 virtual Addr branchTarget(ThreadContext *tc) const;
396 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
416
417 /**
418 * Return true if the instruction is a control transfer, and if so,
419 * return the target address as well.
420 */
397
398 /**
399 * Return true if the instruction is a control transfer, and if so,
400 * return the target address as well.
401 */
421 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
402 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
403 TheISA::PCState &tgt) const;
422
423 /**
424 * Return string representation of disassembled instruction.
425 * The default version of this function will call the internal
426 * virtual generateDisassembly() function to get the string,
427 * then cache it in #cachedDisassembly. If the disassembly
428 * should not be cached, this function should be overridden directly.
429 */

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405 /**
406 * Return string representation of disassembled instruction.
407 * The default version of this function will call the internal
408 * virtual generateDisassembly() function to get the string,
409 * then cache it in #cachedDisassembly. If the disassembly
410 * should not be cached, this function should be overridden directly.
411 */

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