static_inst.hh (5865:54ed46881217) static_inst.hh (5870:5645632d594c)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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377
378 /// Constructor.
379 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
380 : StaticInstBase(__opClass),
381 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
382 { }
383
384 public:
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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377
378 /// Constructor.
379 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
380 : StaticInstBase(__opClass),
381 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
382 { }
383
384 public:
385 virtual ~StaticInst();
385
386
386 virtual ~StaticInst()
387 {
388 if (cachedDisassembly)
389 delete cachedDisassembly;
390 }
391
392/**
393 * The execute() signatures are auto-generated by scons based on the
394 * set of CPU models we are compiling in today.
395 */
396#include "cpu/static_inst_exec_sigs.hh"
397
398 /**
399 * Return the microop that goes with a particular micropc. This should
400 * only be defined/used in macroops which will contain microops
401 */
402 virtual StaticInstPtr fetchMicroop(MicroPC micropc);
403
404 /**
405 * Return the target address for a PC-relative branch.
406 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
407 * should be true).
408 */
387/**
388 * The execute() signatures are auto-generated by scons based on the
389 * set of CPU models we are compiling in today.
390 */
391#include "cpu/static_inst_exec_sigs.hh"
392
393 /**
394 * Return the microop that goes with a particular micropc. This should
395 * only be defined/used in macroops which will contain microops
396 */
397 virtual StaticInstPtr fetchMicroop(MicroPC micropc);
398
399 /**
400 * Return the target address for a PC-relative branch.
401 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
402 * should be true).
403 */
409 virtual Addr branchTarget(Addr branchPC) const
410 {
411 panic("StaticInst::branchTarget() called on instruction "
412 "that is not a PC-relative branch.");
413 M5_DUMMY_RETURN
414 }
404 virtual Addr branchTarget(Addr branchPC) const;
415
416 /**
417 * Return the target address for an indirect branch (jump). The
418 * register value is read from the supplied thread context, so
419 * the result is valid only if the thread context is about to
420 * execute the branch in question. Invalid if not an indirect
421 * branch (i.e. isIndirectCtrl() should be true).
422 */
405
406 /**
407 * Return the target address for an indirect branch (jump). The
408 * register value is read from the supplied thread context, so
409 * the result is valid only if the thread context is about to
410 * execute the branch in question. Invalid if not an indirect
411 * branch (i.e. isIndirectCtrl() should be true).
412 */
423 virtual Addr branchTarget(ThreadContext *tc) const
424 {
425 panic("StaticInst::branchTarget() called on instruction "
426 "that is not an indirect branch.");
427 M5_DUMMY_RETURN
428 }
413 virtual Addr branchTarget(ThreadContext *tc) const;
429
430 /**
431 * Return true if the instruction is a control transfer, and if so,
432 * return the target address as well.
433 */
434 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
435
414
415 /**
416 * Return true if the instruction is a control transfer, and if so,
417 * return the target address as well.
418 */
419 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
420
436 virtual Request::Flags memAccFlags()
437 {
438 panic("StaticInst::memAccFlags called on non-memory instruction");
439 return 0;
440 };
421 virtual Request::Flags memAccFlags();
441
442 /**
443 * Return string representation of disassembled instruction.
444 * The default version of this function will call the internal
445 * virtual generateDisassembly() function to get the string,
446 * then cache it in #cachedDisassembly. If the disassembly
447 * should not be cached, this function should be overridden directly.
448 */
449 virtual const std::string &disassemble(Addr pc,
422
423 /**
424 * Return string representation of disassembled instruction.
425 * The default version of this function will call the internal
426 * virtual generateDisassembly() function to get the string,
427 * then cache it in #cachedDisassembly. If the disassembly
428 * should not be cached, this function should be overridden directly.
429 */
430 virtual const std::string &disassemble(Addr pc,
450 const SymbolTable *symtab = 0) const
451 {
452 if (!cachedDisassembly)
453 cachedDisassembly =
454 new std::string(generateDisassembly(pc, symtab));
431 const SymbolTable *symtab = 0) const;
455
432
456 return *cachedDisassembly;
457 }
458
459 /// Decoded instruction cache type.
460 /// For now we're using a generic hash_map; this seems to work
461 /// pretty well.
462 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
463
464 /// A cache of decoded instruction objects.
465 static DecodeCache decodeCache;
466

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481
482 /// Decoded instruction cache type, for address decoding.
483 /// A generic hash_map is used.
484 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
485
486 /// A cache of decoded instruction objects from addresses.
487 static AddrDecodeCache addrDecodeCache;
488
433 /// Decoded instruction cache type.
434 /// For now we're using a generic hash_map; this seems to work
435 /// pretty well.
436 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
437
438 /// A cache of decoded instruction objects.
439 static DecodeCache decodeCache;
440

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455
456 /// Decoded instruction cache type, for address decoding.
457 /// A generic hash_map is used.
458 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
459
460 /// A cache of decoded instruction objects from addresses.
461 static AddrDecodeCache addrDecodeCache;
462
489 struct cacheElement {
463 struct cacheElement
464 {
490 Addr page_addr;
491 AddrDecodePage *decodePage;
492
465 Addr page_addr;
466 AddrDecodePage *decodePage;
467
493 cacheElement()
494 :decodePage(NULL) { }
495 } ;
468 cacheElement() : decodePage(NULL) { }
469 };
496
497 /// An array of recently decoded instructions.
498 // might not use an array if there is only two elements
499 static struct cacheElement recentDecodes[2];
500
501 /// Updates the recently decoded instructions entries
502 /// @param page_addr The page address recently used.
503 /// @param decodePage Pointer to decoding page containing the decoded

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516 /// Otherwise, we get the instruction from the cache and move it into
517 /// the address-to-instruction decoding page.
518 /// @param mach_inst The binary instruction to decode.
519 /// @param addr The address that contained the binary instruction.
520 /// @param decodePage Pointer to decoding page containing the instruction.
521 /// @retval A pointer to the corresponding StaticInst object.
522 //This is defined as inlined below.
523 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
470
471 /// An array of recently decoded instructions.
472 // might not use an array if there is only two elements
473 static struct cacheElement recentDecodes[2];
474
475 /// Updates the recently decoded instructions entries
476 /// @param page_addr The page address recently used.
477 /// @param decodePage Pointer to decoding page containing the decoded

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490 /// Otherwise, we get the instruction from the cache and move it into
491 /// the address-to-instruction decoding page.
492 /// @param mach_inst The binary instruction to decode.
493 /// @param addr The address that contained the binary instruction.
494 /// @param decodePage Pointer to decoding page containing the instruction.
495 /// @retval A pointer to the corresponding StaticInst object.
496 //This is defined as inlined below.
497 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
524 AddrDecodePage * decodePage);
498 AddrDecodePage *decodePage);
525};
526
527typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
528
529/// Reference-counted pointer to a StaticInst object.
530/// This type should be used instead of "StaticInst *" so that
531/// StaticInst objects can be properly reference-counted.
532class StaticInstPtr : public RefCountingPtr<StaticInst>

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570 typedef TheISA::ExtMachInst ExtMachInst;
571 protected:
572 StaticInstPtr instructions[TheISA::PageBytes];
573 bool valid[TheISA::PageBytes];
574 Addr lowerMask;
575
576 public:
577 /// Constructor
499};
500
501typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
502
503/// Reference-counted pointer to a StaticInst object.
504/// This type should be used instead of "StaticInst *" so that
505/// StaticInst objects can be properly reference-counted.
506class StaticInstPtr : public RefCountingPtr<StaticInst>

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544 typedef TheISA::ExtMachInst ExtMachInst;
545 protected:
546 StaticInstPtr instructions[TheISA::PageBytes];
547 bool valid[TheISA::PageBytes];
548 Addr lowerMask;
549
550 public:
551 /// Constructor
578 AddrDecodePage() {
552 AddrDecodePage()
553 {
579 lowerMask = TheISA::PageBytes - 1;
580 memset(valid, 0, TheISA::PageBytes);
581 }
582
583 /// Checks if the instruction is already decoded and the machine
584 /// instruction in the cache matches the current machine instruction
585 /// related to the address
586 /// @param mach_inst The binary instruction to check
587 /// @param addr The address containing the instruction
554 lowerMask = TheISA::PageBytes - 1;
555 memset(valid, 0, TheISA::PageBytes);
556 }
557
558 /// Checks if the instruction is already decoded and the machine
559 /// instruction in the cache matches the current machine instruction
560 /// related to the address
561 /// @param mach_inst The binary instruction to check
562 /// @param addr The address containing the instruction
588 inline bool decoded(ExtMachInst mach_inst, Addr addr)
563 bool
564 decoded(ExtMachInst mach_inst, Addr addr)
589 {
590 return (valid[addr & lowerMask] &&
591 (instructions[addr & lowerMask]->machInst == mach_inst));
592 }
593
594 /// Returns the instruction object. decoded should be called first
595 /// to check if the instruction is valid.
596 /// @param addr The address of the instruction.
597 /// @retval A pointer to the corresponding StaticInst object.
565 {
566 return (valid[addr & lowerMask] &&
567 (instructions[addr & lowerMask]->machInst == mach_inst));
568 }
569
570 /// Returns the instruction object. decoded should be called first
571 /// to check if the instruction is valid.
572 /// @param addr The address of the instruction.
573 /// @retval A pointer to the corresponding StaticInst object.
598 inline StaticInstPtr getInst(Addr addr)
599 { return instructions[addr & lowerMask]; }
574 StaticInstPtr
575 getInst(Addr addr)
576 {
577 return instructions[addr & lowerMask];
578 }
600
601 /// Inserts a pointer to a StaticInst object into the list of decoded
602 /// instructions on the page.
603 /// @param addr The address of the instruction.
604 /// @param si A pointer to the corresponding StaticInst object.
579
580 /// Inserts a pointer to a StaticInst object into the list of decoded
581 /// instructions on the page.
582 /// @param addr The address of the instruction.
583 /// @param si A pointer to the corresponding StaticInst object.
605 inline void insert(Addr addr, StaticInstPtr &si)
584 void
585 insert(Addr addr, StaticInstPtr &si)
606 {
607 instructions[addr & lowerMask] = si;
608 valid[addr & lowerMask] = true;
609 }
586 {
587 instructions[addr & lowerMask] = si;
588 valid[addr & lowerMask] = true;
589 }
610
611};
612
613
614inline StaticInstPtr
615StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
616{
617#ifdef DECODE_CACHE_HASH_STATS
618 // Simple stats on decode hash_map. Turns out the default

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651 updateCache(page_addr, iter->second);
652 if (iter->second->decoded(mach_inst, addr))
653 return iter->second->getInst(addr);
654
655 return searchCache(mach_inst, addr, iter->second);
656 }
657
658 // creates a new object for a page of decoded instructions
590};
591
592
593inline StaticInstPtr
594StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
595{
596#ifdef DECODE_CACHE_HASH_STATS
597 // Simple stats on decode hash_map. Turns out the default

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630 updateCache(page_addr, iter->second);
631 if (iter->second->decoded(mach_inst, addr))
632 return iter->second->getInst(addr);
633
634 return searchCache(mach_inst, addr, iter->second);
635 }
636
637 // creates a new object for a page of decoded instructions
659 AddrDecodePage * decodePage = new AddrDecodePage;
638 AddrDecodePage *decodePage = new AddrDecodePage;
660 addrDecodeCache[page_addr] = decodePage;
661 updateCache(page_addr, decodePage);
662 return searchCache(mach_inst, addr, decodePage);
663}
664
665inline StaticInstPtr
666StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
639 addrDecodeCache[page_addr] = decodePage;
640 updateCache(page_addr, decodePage);
641 return searchCache(mach_inst, addr, decodePage);
642}
643
644inline StaticInstPtr
645StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
667 AddrDecodePage * decodePage)
646 AddrDecodePage *decodePage)
668{
669 DecodeCache::iterator iter = decodeCache.find(mach_inst);
670 if (iter != decodeCache.end()) {
671 decodePage->insert(addr, iter->second);
672 return iter->second;
673 }
674
675 StaticInstPtr si = TheISA::decodeInst(mach_inst);
676 decodePage->insert(addr, si);
677 decodeCache[mach_inst] = si;
678 return si;
679}
680
681#endif // __CPU_STATIC_INST_HH__
647{
648 DecodeCache::iterator iter = decodeCache.find(mach_inst);
649 if (iter != decodeCache.end()) {
650 decodePage->insert(addr, iter->second);
651 return iter->second;
652 }
653
654 StaticInstPtr si = TheISA::decodeInst(mach_inst);
655 decodePage->insert(addr, si);
656 decodeCache[mach_inst] = si;
657 return si;
658}
659
660#endif // __CPU_STATIC_INST_HH__