static_inst.hh (5677:c8479d55206c) static_inst.hh (5865:54ed46881217)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56class O3CPUImpl;
57template <class Impl> class BaseO3DynInst;
58typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56class O3CPUImpl;
57template <class Impl> class BaseO3DynInst;
58typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
59template <class Impl> class OzoneDynInst;
60class InOrderDynInst;
59
61
60template <class Impl>
61class OzoneDynInst;
62
63class CheckerCPU;
64class FastCPU;
65class AtomicSimpleCPU;
66class TimingSimpleCPU;
67class InorderCPU;
68class SymbolTable;
69class AddrDecodePage;
70

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429 }
430
431 /**
432 * Return true if the instruction is a control transfer, and if so,
433 * return the target address as well.
434 */
435 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
436
62class CheckerCPU;
63class FastCPU;
64class AtomicSimpleCPU;
65class TimingSimpleCPU;
66class InorderCPU;
67class SymbolTable;
68class AddrDecodePage;
69

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428 }
429
430 /**
431 * Return true if the instruction is a control transfer, and if so,
432 * return the target address as well.
433 */
434 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
435
436 virtual Request::Flags memAccFlags()
437 {
438 panic("StaticInst::memAccFlags called on non-memory instruction");
439 return 0;
440 };
441
437 /**
438 * Return string representation of disassembled instruction.
439 * The default version of this function will call the internal
440 * virtual generateDisassembly() function to get the string,
441 * then cache it in #cachedDisassembly. If the disassembly
442 * should not be cached, this function should be overridden directly.
443 */
444 virtual const std::string &disassemble(Addr pc,

--- 232 unchanged lines hidden --- 		442 /**
443 * Return string representation of disassembled instruction.
444 * The default version of this function will call the internal
445 * virtual generateDisassembly() function to get the string,
446 * then cache it in #cachedDisassembly. If the disassembly
447 * should not be cached, this function should be overridden directly.
448 */
449 virtual const std::string &disassemble(Addr pc,

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