static_inst.hh (4182:5b2c0d266107) static_inst.hh (4539:6eeeea62b7c4)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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138
139 IsNonSpeculative, ///< Should not be executed speculatively
140 IsQuiesce, ///< Is a quiesce instruction
141
142 IsIprAccess, ///< Accesses IPRs
143 IsUnverifiable, ///< Can't be verified by a checker
144
145 //Flags for microcode
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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138
139 IsNonSpeculative, ///< Should not be executed speculatively
140 IsQuiesce, ///< Is a quiesce instruction
141
142 IsIprAccess, ///< Accesses IPRs
143 IsUnverifiable, ///< Can't be verified by a checker
144
145 //Flags for microcode
146 IsMacroOp, ///< Is a macroop containing microops
147 IsMicroOp, ///< Is a microop
146 IsMacroop, ///< Is a macroop containing microops
147 IsMicroop, ///< Is a microop
148 IsDelayedCommit, ///< This microop doesn't commit right away
148 IsDelayedCommit, ///< This microop doesn't commit right away
149 IsLastMicroOp, ///< This microop ends a microop sequence
150 IsFirstMicroOp, ///< This microop begins a microop sequence
149 IsLastMicroop, ///< This microop ends a microop sequence
150 IsFirstMicroop, ///< This microop begins a microop sequence
151 //This flag doesn't do anything yet
152 IsMicroBranch, ///< This microop branches within the microcode for a macroop
153
154 NumFlags
155 };
156
157 /// Flag values for this instruction.
158 std::bitset<NumFlags> flags;

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237 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
238 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
239 bool isMemBarrier() const { return flags[IsMemBarrier]; }
240 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
241 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
242 bool isQuiesce() const { return flags[IsQuiesce]; }
243 bool isIprAccess() const { return flags[IsIprAccess]; }
244 bool isUnverifiable() const { return flags[IsUnverifiable]; }
151 //This flag doesn't do anything yet
152 IsMicroBranch, ///< This microop branches within the microcode for a macroop
153
154 NumFlags
155 };
156
157 /// Flag values for this instruction.
158 std::bitset<NumFlags> flags;

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237 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
238 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
239 bool isMemBarrier() const { return flags[IsMemBarrier]; }
240 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
241 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
242 bool isQuiesce() const { return flags[IsQuiesce]; }
243 bool isIprAccess() const { return flags[IsIprAccess]; }
244 bool isUnverifiable() const { return flags[IsUnverifiable]; }
245 bool isMacroOp() const { return flags[IsMacroOp]; }
246 bool isMicroOp() const { return flags[IsMicroOp]; }
245 bool isMacroop() const { return flags[IsMacroop]; }
246 bool isMicroop() const { return flags[IsMicroop]; }
247 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
247 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
248 bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
249 bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
248 bool isLastMicroop() const { return flags[IsLastMicroop]; }
249 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
250 //This flag doesn't do anything yet
251 bool isMicroBranch() const { return flags[IsMicroBranch]; }
252 //@}
253
254 /// Operation class. Used to select appropriate function unit in issue.
255 OpClass opClass() const { return _opClass; }
256};
257

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364 * set of CPU models we are compiling in today.
365 */
366#include "cpu/static_inst_exec_sigs.hh"
367
368 /**
369 * Return the microop that goes with a particular micropc. This should
370 * only be defined/used in macroops which will contain microops
371 */
250 //This flag doesn't do anything yet
251 bool isMicroBranch() const { return flags[IsMicroBranch]; }
252 //@}
253
254 /// Operation class. Used to select appropriate function unit in issue.
255 OpClass opClass() const { return _opClass; }
256};
257

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364 * set of CPU models we are compiling in today.
365 */
366#include "cpu/static_inst_exec_sigs.hh"
367
368 /**
369 * Return the microop that goes with a particular micropc. This should
370 * only be defined/used in macroops which will contain microops
371 */
372 virtual StaticInstPtr fetchMicroOp(MicroPC micropc);
372 virtual StaticInstPtr fetchMicroop(MicroPC micropc);
373
374 /**
375 * Return the target address for a PC-relative branch.
376 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
377 * should be true).
378 */
379 virtual Addr branchTarget(Addr branchPC) const
380 {

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374 /**
375 * Return the target address for a PC-relative branch.
376 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
377 * should be true).
378 */
379 virtual Addr branchTarget(Addr branchPC) const
380 {

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