static_inst.hh (2985:c010893f23ae) static_inst.hh (3271:4a871cbe6d84)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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62class TimingSimpleCPU;
63class InorderCPU;
64class SymbolTable;
65
66namespace Trace {
67 class InstRecord;
68}
69
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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62class TimingSimpleCPU;
63class InorderCPU;
64class SymbolTable;
65
66namespace Trace {
67 class InstRecord;
68}
69
70typedef uint32_t MicroPC;
71
70/**
71 * Base, ISA-independent static instruction class.
72 *
73 * The main component of this class is the vector of flags and the
74 * associated methods for reading them. Any object that can rely
75 * solely on these flags can process instructions without being
76 * recompiled for multiple ISAs.
77 */

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134 IsWriteBarrier, ///< Is a write barrier
135
136 IsNonSpeculative, ///< Should not be executed speculatively
137 IsQuiesce, ///< Is a quiesce instruction
138
139 IsIprAccess, ///< Accesses IPRs
140 IsUnverifiable, ///< Can't be verified by a checker
141
72/**
73 * Base, ISA-independent static instruction class.
74 *
75 * The main component of this class is the vector of flags and the
76 * associated methods for reading them. Any object that can rely
77 * solely on these flags can process instructions without being
78 * recompiled for multiple ISAs.
79 */

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136 IsWriteBarrier, ///< Is a write barrier
137
138 IsNonSpeculative, ///< Should not be executed speculatively
139 IsQuiesce, ///< Is a quiesce instruction
140
141 IsIprAccess, ///< Accesses IPRs
142 IsUnverifiable, ///< Can't be verified by a checker
143
144 //Flags for microcode
145 IsMacroOp, ///< Is a macroop containing microops
146 IsMicroOp, ///< Is a microop
147 IsDelayedCommit, ///< This microop doesn't commit right away
148 IsLastMicroOp, ///< This microop ends a microop sequence
149 //This flag doesn't do anything yet
150 IsMicroBranch, ///< This microop branches within the microcode for a macroop
151
142 NumFlags
143 };
144
145 /// Flag values for this instruction.
146 std::bitset<NumFlags> flags;
147
148 /// See opClass().
149 OpClass _opClass;

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225 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
226 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
227 bool isMemBarrier() const { return flags[IsMemBarrier]; }
228 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
229 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
230 bool isQuiesce() const { return flags[IsQuiesce]; }
231 bool isIprAccess() const { return flags[IsIprAccess]; }
232 bool isUnverifiable() const { return flags[IsUnverifiable]; }
152 NumFlags
153 };
154
155 /// Flag values for this instruction.
156 std::bitset<NumFlags> flags;
157
158 /// See opClass().
159 OpClass _opClass;

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235 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
236 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
237 bool isMemBarrier() const { return flags[IsMemBarrier]; }
238 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
239 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
240 bool isQuiesce() const { return flags[IsQuiesce]; }
241 bool isIprAccess() const { return flags[IsIprAccess]; }
242 bool isUnverifiable() const { return flags[IsUnverifiable]; }
243 bool isMacroOp() const { return flags[IsMacroOp]; }
244 bool isMicroOp() const { return flags[IsMicroOp]; }
245 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
246 bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
247 //This flag doesn't do anything yet
248 bool isMicroBranch() const { return flags[IsMicroBranch]; }
233 //@}
234
235 /// Operation class. Used to select appropriate function unit in issue.
236 OpClass opClass() const { return _opClass; }
237};
238
239
240// forward declaration

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342
343/**
344 * The execute() signatures are auto-generated by scons based on the
345 * set of CPU models we are compiling in today.
346 */
347#include "cpu/static_inst_exec_sigs.hh"
348
349 /**
249 //@}
250
251 /// Operation class. Used to select appropriate function unit in issue.
252 OpClass opClass() const { return _opClass; }
253};
254
255
256// forward declaration

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358
359/**
360 * The execute() signatures are auto-generated by scons based on the
361 * set of CPU models we are compiling in today.
362 */
363#include "cpu/static_inst_exec_sigs.hh"
364
365 /**
366 * Return the microop that goes with a particular micropc. This should
367 * only be defined/used in macroops which will contain microops
368 */
369 virtual StaticInstPtr fetchMicroOp(MicroPC micropc);
370
371 /**
350 * Return the target address for a PC-relative branch.
351 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
352 * should be true).
353 */
354 virtual Addr branchTarget(Addr branchPC) const
355 {
356 panic("StaticInst::branchTarget() called on instruction "
357 "that is not a PC-relative branch.");

--- 131 unchanged lines hidden --- 		372 * Return the target address for a PC-relative branch.
373 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
374 * should be true).
375 */
376 virtual Addr branchTarget(Addr branchPC) const
377 {
378 panic("StaticInst::branchTarget() called on instruction "
379 "that is not a PC-relative branch.");

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