static_inst.hh (2670:9107b8bd08cd) static_inst.hh (2680:246e7104f744)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40#include "cpu/op_class.hh"
41#include "sim/host.hh"
42#include "arch/isa_traits.hh"
43
44// forward declarations
45struct AlphaSimpleImpl;
46struct OzoneImpl;
47struct SimpleImpl;
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40#include "cpu/op_class.hh"
41#include "sim/host.hh"
42#include "arch/isa_traits.hh"
43
44// forward declarations
45struct AlphaSimpleImpl;
46struct OzoneImpl;
47struct SimpleImpl;
48class ExecContext;
48class ThreadContext;
49class DynInst;
50class Packet;
51
52template <class Impl>
53class AlphaDynInst;
54
55template <class Impl>
56class OzoneDynInst;

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352 virtual Addr branchTarget(Addr branchPC) const
353 {
354 panic("StaticInst::branchTarget() called on instruction "
355 "that is not a PC-relative branch.");
356 }
357
358 /**
359 * Return the target address for an indirect branch (jump). The
49class DynInst;
50class Packet;
51
52template <class Impl>
53class AlphaDynInst;
54
55template <class Impl>
56class OzoneDynInst;

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352 virtual Addr branchTarget(Addr branchPC) const
353 {
354 panic("StaticInst::branchTarget() called on instruction "
355 "that is not a PC-relative branch.");
356 }
357
358 /**
359 * Return the target address for an indirect branch (jump). The
360 * register value is read from the supplied execution context, so
361 * the result is valid only if the execution context is about to
360 * register value is read from the supplied thread context, so
361 * the result is valid only if the thread context is about to
362 * execute the branch in question. Invalid if not an indirect
363 * branch (i.e. isIndirectCtrl() should be true).
364 */
362 * execute the branch in question. Invalid if not an indirect
363 * branch (i.e. isIndirectCtrl() should be true).
364 */
365 virtual Addr branchTarget(ExecContext *xc) const
365 virtual Addr branchTarget(ThreadContext *tc) const
366 {
367 panic("StaticInst::branchTarget() called on instruction "
368 "that is not an indirect branch.");
369 }
370
371 /**
372 * Return true if the instruction is a control transfer, and if so,
373 * return the target address as well.
374 */
366 {
367 panic("StaticInst::branchTarget() called on instruction "
368 "that is not an indirect branch.");
369 }
370
371 /**
372 * Return true if the instruction is a control transfer, and if so,
373 * return the target address as well.
374 */
375 bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
375 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
376
377 /**
378 * Return string representation of disassembled instruction.
379 * The default version of this function will call the internal
380 * virtual generateDisassembly() function to get the string,
381 * then cache it in #cachedDisassembly. If the disassembly
382 * should not be cached, this function should be overridden directly.
383 */

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377 /**
378 * Return string representation of disassembled instruction.
379 * The default version of this function will call the internal
380 * virtual generateDisassembly() function to get the string,
381 * then cache it in #cachedDisassembly. If the disassembly
382 * should not be cached, this function should be overridden directly.
383 */

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