static_inst.hh (2654:9559cfa91b9d) | static_inst.hh (2665:a124942bacb8) |
---|---|
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Steve Reinhardt |
|
27 */ 28 29#ifndef __CPU_STATIC_INST_HH__ 30#define __CPU_STATIC_INST_HH__ 31 32#include <bitset> 33#include <string> 34 35#include "base/hashmap.hh" 36#include "base/misc.hh" 37#include "base/refcnt.hh" 38#include "cpu/op_class.hh" 39#include "sim/host.hh" 40#include "arch/isa_traits.hh" 41 42// forward declarations 43struct AlphaSimpleImpl; | 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "base/hashmap.hh" 38#include "base/misc.hh" 39#include "base/refcnt.hh" 40#include "cpu/op_class.hh" 41#include "sim/host.hh" 42#include "arch/isa_traits.hh" 43 44// forward declarations 45struct AlphaSimpleImpl; |
44struct OzoneImpl; 45struct SimpleImpl; | |
46class ExecContext; 47class DynInst; 48class Packet; 49 50template <class Impl> 51class AlphaDynInst; 52 | 46class ExecContext; 47class DynInst; 48class Packet; 49 50template <class Impl> 51class AlphaDynInst; 52 |
53template <class Impl> 54class OzoneDynInst; 55 56class CheckerCPU; | |
57class FastCPU; 58class AtomicSimpleCPU; 59class TimingSimpleCPU; 60class InorderCPU; 61class SymbolTable; 62 63namespace Trace { 64 class InstRecord; --- 36 unchanged lines hidden (view full) --- 101 IsNop, ///< Is a no-op (no effect at all). 102 103 IsInteger, ///< References integer regs. 104 IsFloating, ///< References FP regs. 105 106 IsMemRef, ///< References memory (load, store, or prefetch). 107 IsLoad, ///< Reads from memory (load or prefetch). 108 IsStore, ///< Writes to memory. | 53class FastCPU; 54class AtomicSimpleCPU; 55class TimingSimpleCPU; 56class InorderCPU; 57class SymbolTable; 58 59namespace Trace { 60 class InstRecord; --- 36 unchanged lines hidden (view full) --- 97 IsNop, ///< Is a no-op (no effect at all). 98 99 IsInteger, ///< References integer regs. 100 IsFloating, ///< References FP regs. 101 102 IsMemRef, ///< References memory (load, store, or prefetch). 103 IsLoad, ///< Reads from memory (load or prefetch). 104 IsStore, ///< Writes to memory. |
109 IsStoreConditional, ///< Store conditional instruction. | |
110 IsInstPrefetch, ///< Instruction-cache prefetch. 111 IsDataPrefetch, ///< Data-cache prefetch. 112 IsCopy, ///< Fast Cache block copy 113 114 IsControl, ///< Control transfer instruction. 115 IsDirectControl, ///< PC relative control transfer. 116 IsIndirectControl, ///< Register indirect control transfer. 117 IsCondControl, ///< Conditional control transfer. --- 8 unchanged lines hidden (view full) --- 126 IsSerializing, ///< Serializes pipeline: won't execute until all 127 /// older instructions have committed. 128 IsSerializeBefore, 129 IsSerializeAfter, 130 IsMemBarrier, ///< Is a memory barrier 131 IsWriteBarrier, ///< Is a write barrier 132 133 IsNonSpeculative, ///< Should not be executed speculatively | 105 IsInstPrefetch, ///< Instruction-cache prefetch. 106 IsDataPrefetch, ///< Data-cache prefetch. 107 IsCopy, ///< Fast Cache block copy 108 109 IsControl, ///< Control transfer instruction. 110 IsDirectControl, ///< PC relative control transfer. 111 IsIndirectControl, ///< Register indirect control transfer. 112 IsCondControl, ///< Conditional control transfer. --- 8 unchanged lines hidden (view full) --- 121 IsSerializing, ///< Serializes pipeline: won't execute until all 122 /// older instructions have committed. 123 IsSerializeBefore, 124 IsSerializeAfter, 125 IsMemBarrier, ///< Is a memory barrier 126 IsWriteBarrier, ///< Is a write barrier 127 128 IsNonSpeculative, ///< Should not be executed speculatively |
134 IsQuiesce, ///< Is a quiesce instruction | |
135 | 129 |
136 IsIprAccess, ///< Accesses IPRs 137 IsUnverifiable, ///< Can't be verified by a checker 138 | |
139 NumFlags 140 }; 141 142 /// Flag values for this instruction. 143 std::bitset<NumFlags> flags; 144 145 /// See opClass(). 146 OpClass _opClass; --- 46 unchanged lines hidden (view full) --- 193 /// of the individual flags. 194 //@{ 195 196 bool isNop() const { return flags[IsNop]; } 197 198 bool isMemRef() const { return flags[IsMemRef]; } 199 bool isLoad() const { return flags[IsLoad]; } 200 bool isStore() const { return flags[IsStore]; } | 130 NumFlags 131 }; 132 133 /// Flag values for this instruction. 134 std::bitset<NumFlags> flags; 135 136 /// See opClass(). 137 OpClass _opClass; --- 46 unchanged lines hidden (view full) --- 184 /// of the individual flags. 185 //@{ 186 187 bool isNop() const { return flags[IsNop]; } 188 189 bool isMemRef() const { return flags[IsMemRef]; } 190 bool isLoad() const { return flags[IsLoad]; } 191 bool isStore() const { return flags[IsStore]; } |
201 bool isStoreConditional() const { return flags[IsStoreConditional]; } | |
202 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 203 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 204 bool isCopy() const { return flags[IsCopy];} 205 206 bool isInteger() const { return flags[IsInteger]; } 207 bool isFloating() const { return flags[IsFloating]; } 208 209 bool isControl() const { return flags[IsControl]; } --- 8 unchanged lines hidden (view full) --- 218 bool isSerializing() const { return flags[IsSerializing] || 219 flags[IsSerializeBefore] || 220 flags[IsSerializeAfter]; } 221 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 222 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 223 bool isMemBarrier() const { return flags[IsMemBarrier]; } 224 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 225 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } | 192 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 193 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 194 bool isCopy() const { return flags[IsCopy];} 195 196 bool isInteger() const { return flags[IsInteger]; } 197 bool isFloating() const { return flags[IsFloating]; } 198 199 bool isControl() const { return flags[IsControl]; } --- 8 unchanged lines hidden (view full) --- 208 bool isSerializing() const { return flags[IsSerializing] || 209 flags[IsSerializeBefore] || 210 flags[IsSerializeAfter]; } 211 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 212 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 213 bool isMemBarrier() const { return flags[IsMemBarrier]; } 214 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 215 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } |
226 bool isQuiesce() const { return flags[IsQuiesce]; } 227 bool isIprAccess() const { return flags[IsIprAccess]; } 228 bool isUnverifiable() const { return flags[IsUnverifiable]; } | |
229 //@} 230 231 /// Operation class. Used to select appropriate function unit in issue. 232 OpClass opClass() const { return _opClass; } 233}; 234 235 236// forward declaration --- 254 unchanged lines hidden --- | 216 //@} 217 218 /// Operation class. Used to select appropriate function unit in issue. 219 OpClass opClass() const { return _opClass; } 220}; 221 222 223// forward declaration --- 254 unchanged lines hidden --- |