static_inst.hh (12334:e0ab29a34764) static_inst.hh (12385:288c62455dde)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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198 /// Only the entries from 0 through numDestRegs()-1 are valid.
199 const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
200
201 /// Return logical index (architectural reg num) of i'th source reg.
202 /// Only the entries from 0 through numSrcRegs()-1 are valid.
203 const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
204
205 /// Pointer to a statically allocated "null" instruction object.
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 189 unchanged lines hidden (view full) ---

198 /// Only the entries from 0 through numDestRegs()-1 are valid.
199 const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
200
201 /// Return logical index (architectural reg num) of i'th source reg.
202 /// Only the entries from 0 through numSrcRegs()-1 are valid.
203 const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
204
205 /// Pointer to a statically allocated "null" instruction object.
206 /// Used to give eaCompInst() and memAccInst() something to return
207 /// when called on non-memory instructions.
208 static StaticInstPtr nullStaticInstPtr;
209
206 static StaticInstPtr nullStaticInstPtr;
207
210 /**
211 * Memory references only: returns "fake" instruction representing
212 * the effective address part of the memory operation. Used to
213 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
214 * just the EA computation.
215 */
216 virtual const
217 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
218
219 /**
220 * Memory references only: returns "fake" instruction representing
221 * the memory access part of the memory operation. Used to
222 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
223 * just the memory access (not the EA computation).
224 */
225 virtual const
226 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
227
228 /// The binary machine instruction.
229 const ExtMachInst machInst;
230
231 protected:
232
233 /// See destRegIdx().
234 RegId _destRegIdx[MaxInstDestRegs];
235 /// See srcRegIdx().

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267 mnemonic(_mnemonic), cachedDisassembly(0)
268 { }
269
270 public:
271 virtual ~StaticInst();
272
273 virtual Fault execute(ExecContext *xc,
274 Trace::InstRecord *traceData) const = 0;
208 /// The binary machine instruction.
209 const ExtMachInst machInst;
210
211 protected:
212
213 /// See destRegIdx().
214 RegId _destRegIdx[MaxInstDestRegs];
215 /// See srcRegIdx().

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247 mnemonic(_mnemonic), cachedDisassembly(0)
248 { }
249
250 public:
251 virtual ~StaticInst();
252
253 virtual Fault execute(ExecContext *xc,
254 Trace::InstRecord *traceData) const = 0;
275 virtual Fault eaComp(ExecContext *xc,
276 Trace::InstRecord *traceData) const
277 {
278 panic("eaComp not defined!");
279 }
280
281 virtual Fault initiateAcc(ExecContext *xc,
282 Trace::InstRecord *traceData) const
283 {
284 panic("initiateAcc not defined!");
285 }
286
287 virtual Fault completeAcc(Packet *pkt, ExecContext *xc,

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256 virtual Fault initiateAcc(ExecContext *xc,
257 Trace::InstRecord *traceData) const
258 {
259 panic("initiateAcc not defined!");
260 }
261
262 virtual Fault completeAcc(Packet *pkt, ExecContext *xc,

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