static_inst.hh (10935:acd48ddd725f) static_inst.hh (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/reg_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
48
49// forward declarations
50class Packet;
51
52class ExecContext;

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65 * solely on these flags can process instructions without being
66 * recompiled for multiple ISAs.
67 */
68class StaticInst : public RefCounted, public StaticInstFlags
69{
70 public:
71 /// Binary extended machine instruction type.
72 typedef TheISA::ExtMachInst ExtMachInst;
46#include "cpu/static_inst_fwd.hh"
47#include "cpu/thread_context.hh"
48#include "enums/StaticInstFlags.hh"
49
50// forward declarations
51class Packet;
52
53class ExecContext;

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66 * solely on these flags can process instructions without being
67 * recompiled for multiple ISAs.
68 */
69class StaticInst : public RefCounted, public StaticInstFlags
70{
71 public:
72 /// Binary extended machine instruction type.
73 typedef TheISA::ExtMachInst ExtMachInst;
73 /// Logical register index type.
74 typedef TheISA::RegIndex RegIndex;
75
76 enum {
77 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
78 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
79 };
80
81 protected:
82

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180 void setFlag(Flags f) { flags[f] = true; }
181
182 /// Operation class. Used to select appropriate function unit in issue.
183 OpClass opClass() const { return _opClass; }
184
185
186 /// Return logical index (architectural reg num) of i'th destination reg.
187 /// Only the entries from 0 through numDestRegs()-1 are valid.
74
75 enum {
76 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
77 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
78 };
79
80 protected:
81

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179 void setFlag(Flags f) { flags[f] = true; }
180
181 /// Operation class. Used to select appropriate function unit in issue.
182 OpClass opClass() const { return _opClass; }
183
184
185 /// Return logical index (architectural reg num) of i'th destination reg.
186 /// Only the entries from 0 through numDestRegs()-1 are valid.
188 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
187 RegId destRegIdx(int i) const { return _destRegIdx[i]; }
189
190 /// Return logical index (architectural reg num) of i'th source reg.
191 /// Only the entries from 0 through numSrcRegs()-1 are valid.
188
189 /// Return logical index (architectural reg num) of i'th source reg.
190 /// Only the entries from 0 through numSrcRegs()-1 are valid.
192 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
191 RegId srcRegIdx(int i) const { return _srcRegIdx[i]; }
193
194 /// Pointer to a statically allocated "null" instruction object.
195 /// Used to give eaCompInst() and memAccInst() something to return
196 /// when called on non-memory instructions.
197 static StaticInstPtr nullStaticInstPtr;
198
199 /**
200 * Memory references only: returns "fake" instruction representing

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215 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
216
217 /// The binary machine instruction.
218 const ExtMachInst machInst;
219
220 protected:
221
222 /// See destRegIdx().
192
193 /// Pointer to a statically allocated "null" instruction object.
194 /// Used to give eaCompInst() and memAccInst() something to return
195 /// when called on non-memory instructions.
196 static StaticInstPtr nullStaticInstPtr;
197
198 /**
199 * Memory references only: returns "fake" instruction representing

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214 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
215
216 /// The binary machine instruction.
217 const ExtMachInst machInst;
218
219 protected:
220
221 /// See destRegIdx().
223 RegIndex _destRegIdx[MaxInstDestRegs];
222 RegId _destRegIdx[MaxInstDestRegs];
224 /// See srcRegIdx().
223 /// See srcRegIdx().
225 RegIndex _srcRegIdx[MaxInstSrcRegs];
224 RegId _srcRegIdx[MaxInstSrcRegs];
226
227 /**
228 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
229 * methods. Also useful to readily identify instructions from
230 * within the debugger when #cachedDisassembly has not been
231 * initialized.
232 */
233 const char *mnemonic;

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226 /**
227 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
228 * methods. Also useful to readily identify instructions from
229 * within the debugger when #cachedDisassembly has not been
230 * initialized.
231 */
232 const char *mnemonic;

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