static_inst.hh (10934:5af8f40d8f2c) | static_inst.hh (10935:acd48ddd725f) |
---|---|
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 84 unchanged lines hidden (view full) --- 93 int8_t _numDestRegs; 94 95 /// The following are used to track physical register usage 96 /// for machines with separate int & FP reg files. 97 //@{ 98 int8_t _numFPDestRegs; 99 int8_t _numIntDestRegs; 100 int8_t _numCCDestRegs; | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 84 unchanged lines hidden (view full) --- 93 int8_t _numDestRegs; 94 95 /// The following are used to track physical register usage 96 /// for machines with separate int & FP reg files. 97 //@{ 98 int8_t _numFPDestRegs; 99 int8_t _numIntDestRegs; 100 int8_t _numCCDestRegs; |
101 int8_t _numVectorDestRegs; | |
102 //@} 103 104 public: 105 106 /// @name Register information. 107 /// The sum of numFPDestRegs() and numIntDestRegs() equals 108 /// numDestRegs(). The former two functions are used to track 109 /// physical register usage for machines with separate int & FP 110 /// reg files. 111 //@{ 112 /// Number of source registers. 113 int8_t numSrcRegs() const { return _numSrcRegs; } 114 /// Number of destination registers. 115 int8_t numDestRegs() const { return _numDestRegs; } 116 /// Number of floating-point destination regs. 117 int8_t numFPDestRegs() const { return _numFPDestRegs; } 118 /// Number of integer destination regs. 119 int8_t numIntDestRegs() const { return _numIntDestRegs; } | 101 //@} 102 103 public: 104 105 /// @name Register information. 106 /// The sum of numFPDestRegs() and numIntDestRegs() equals 107 /// numDestRegs(). The former two functions are used to track 108 /// physical register usage for machines with separate int & FP 109 /// reg files. 110 //@{ 111 /// Number of source registers. 112 int8_t numSrcRegs() const { return _numSrcRegs; } 113 /// Number of destination registers. 114 int8_t numDestRegs() const { return _numDestRegs; } 115 /// Number of floating-point destination regs. 116 int8_t numFPDestRegs() const { return _numFPDestRegs; } 117 /// Number of integer destination regs. 118 int8_t numIntDestRegs() const { return _numIntDestRegs; } |
120 /// Number of condition code destination regs. | 119 //@} 120 /// Number of coprocesor destination regs. |
121 int8_t numCCDestRegs() const { return _numCCDestRegs; } | 121 int8_t numCCDestRegs() const { return _numCCDestRegs; } |
122 /// Number of vector destination regs. 123 int8_t numVectorDestRegs() const { return _numVectorDestRegs; } | |
124 //@} 125 126 /// @name Flag accessors. 127 /// These functions are used to access the values of the various 128 /// instruction property flags. See StaticInst::Flags for descriptions 129 /// of the individual flags. 130 //@{ 131 --- 5 unchanged lines hidden (view full) --- 137 bool isStoreConditional() const { return flags[IsStoreConditional]; } 138 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 139 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 140 bool isPrefetch() const { return isInstPrefetch() || 141 isDataPrefetch(); } 142 143 bool isInteger() const { return flags[IsInteger]; } 144 bool isFloating() const { return flags[IsFloating]; } | 122 //@} 123 124 /// @name Flag accessors. 125 /// These functions are used to access the values of the various 126 /// instruction property flags. See StaticInst::Flags for descriptions 127 /// of the individual flags. 128 //@{ 129 --- 5 unchanged lines hidden (view full) --- 135 bool isStoreConditional() const { return flags[IsStoreConditional]; } 136 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 137 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 138 bool isPrefetch() const { return isInstPrefetch() || 139 isDataPrefetch(); } 140 141 bool isInteger() const { return flags[IsInteger]; } 142 bool isFloating() const { return flags[IsFloating]; } |
145 bool isVector() const { return flags[IsVector]; } | |
146 bool isCC() const { return flags[IsCC]; } 147 148 bool isControl() const { return flags[IsControl]; } 149 bool isCall() const { return flags[IsCall]; } 150 bool isReturn() const { return flags[IsReturn]; } 151 bool isDirectCtrl() const { return flags[IsDirectControl]; } 152 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 153 bool isCondCtrl() const { return flags[IsCondControl]; } --- 96 unchanged lines hidden (view full) --- 250 /// Constructor. 251 /// It's important to initialize everything here to a sane 252 /// default, since the decoder generally only overrides 253 /// the fields that are meaningful for the particular 254 /// instruction. 255 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 256 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 257 _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0), | 143 bool isCC() const { return flags[IsCC]; } 144 145 bool isControl() const { return flags[IsControl]; } 146 bool isCall() const { return flags[IsCall]; } 147 bool isReturn() const { return flags[IsReturn]; } 148 bool isDirectCtrl() const { return flags[IsDirectControl]; } 149 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 150 bool isCondCtrl() const { return flags[IsCondControl]; } --- 96 unchanged lines hidden (view full) --- 247 /// Constructor. 248 /// It's important to initialize everything here to a sane 249 /// default, since the decoder generally only overrides 250 /// the fields that are meaningful for the particular 251 /// instruction. 252 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 253 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 254 _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0), |
258 _numVectorDestRegs(0), machInst(_machInst), mnemonic(_mnemonic), 259 cachedDisassembly(0) | 255 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) |
260 { } 261 262 public: 263 virtual ~StaticInst(); 264 265 virtual Fault execute(ExecContext *xc, 266 Trace::InstRecord *traceData) const = 0; 267 virtual Fault eaComp(ExecContext *xc, --- 57 unchanged lines hidden (view full) --- 325 326 /** 327 * Print a separator separated list of this instruction's set flag 328 * names on the given stream. 329 */ 330 void printFlags(std::ostream &outs, const std::string &separator) const; 331 332 /// Return name of machine instruction | 256 { } 257 258 public: 259 virtual ~StaticInst(); 260 261 virtual Fault execute(ExecContext *xc, 262 Trace::InstRecord *traceData) const = 0; 263 virtual Fault eaComp(ExecContext *xc, --- 57 unchanged lines hidden (view full) --- 321 322 /** 323 * Print a separator separated list of this instruction's set flag 324 * names on the given stream. 325 */ 326 void printFlags(std::ostream &outs, const std::string &separator) const; 327 328 /// Return name of machine instruction |
333 std::string getName() const { return mnemonic; } | 329 std::string getName() { return mnemonic; } |
334}; 335 336#endif // __CPU_STATIC_INST_HH__ | 330}; 331 332#endif // __CPU_STATIC_INST_HH__ |