static_inst.hh (10259:ebb376f73dd2) static_inst.hh (10319:4207f9bfcceb)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
48#include "sim/fault_fwd.hh"
49
50// forward declarations
51class Packet;
52
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
48#include "sim/fault_fwd.hh"
49
50// forward declarations
51class Packet;
52
53struct O3CPUImpl;
54template <class Impl> class BaseO3DynInst;
55typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
56class InOrderDynInst;
53class ExecContext;
57
54
58class CheckerCPU;
59class AtomicSimpleCPU;
60class TimingSimpleCPU;
61class InorderCPU;
62namespace Minor
63{
64 class ExecContext;
65};
66
67class SymbolTable;
68
69namespace Trace {
70 class InstRecord;
71}
72
73/**
74 * Base, ISA-independent static instruction class.

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262 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
263 _numFPDestRegs(0), _numIntDestRegs(0),
264 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
265 { }
266
267 public:
268 virtual ~StaticInst();
269
55class SymbolTable;
56
57namespace Trace {
58 class InstRecord;
59}
60
61/**
62 * Base, ISA-independent static instruction class.

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250 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
251 _numFPDestRegs(0), _numIntDestRegs(0),
252 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
253 { }
254
255 public:
256 virtual ~StaticInst();
257
270/**
271 * The execute() signatures are auto-generated by scons based on the
272 * set of CPU models we are compiling in today.
273 */
274#include "cpu/static_inst_exec_sigs.hh"
258 virtual Fault execute(ExecContext *xc,
259 Trace::InstRecord *traceData) const = 0;
260 virtual Fault eaComp(ExecContext *xc,
261 Trace::InstRecord *traceData) const
262 {
263 panic("eaComp not defined!");
264 }
275
265
266 virtual Fault initiateAcc(ExecContext *xc,
267 Trace::InstRecord *traceData) const
268 {
269 panic("initiateAcc not defined!");
270 }
271
272 virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
273 Trace::InstRecord *traceData) const
274 {
275 panic("completeAcc not defined!");
276 }
277
276 virtual void advancePC(TheISA::PCState &pcState) const = 0;
277
278 /**
279 * Return the microop that goes with a particular micropc. This should
280 * only be defined/used in macroops which will contain microops
281 */
282 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
283

--- 44 unchanged lines hidden --- 		278 virtual void advancePC(TheISA::PCState &pcState) const = 0;
279
280 /**
281 * Return the microop that goes with a particular micropc. This should
282 * only be defined/used in macroops which will contain microops
283 */
284 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
285

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