1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Steve Reinhardt 30 */ 31 32#ifndef __CPU_STATIC_INST_HH__ 33#define __CPU_STATIC_INST_HH__ 34 35#include <bitset> 36#include <string> 37 38#include "arch/registers.hh" 39#include "arch/types.hh" 40#include "base/logging.hh" 41#include "base/refcnt.hh" 42#include "base/types.hh" 43#include "config/the_isa.hh" 44#include "cpu/op_class.hh" 45#include "cpu/reg_class.hh" 46#include "cpu/reg_class_impl.hh" 47#include "cpu/static_inst_fwd.hh" 48#include "cpu/thread_context.hh" 49#include "enums/StaticInstFlags.hh" 50 51// forward declarations 52class Packet; 53 54class ExecContext; 55 56class SymbolTable; 57 58namespace Trace { 59 class InstRecord; 60} 61 62/** 63 * Base, ISA-independent static instruction class. 64 * 65 * The main component of this class is the vector of flags and the 66 * associated methods for reading them. Any object that can rely 67 * solely on these flags can process instructions without being 68 * recompiled for multiple ISAs. 69 */ 70class StaticInst : public RefCounted, public StaticInstFlags 71{ 72 public: 73 /// Binary extended machine instruction type. 74 typedef TheISA::ExtMachInst ExtMachInst; 75 76 enum { 77 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 78 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 79 }; 80 81 protected: 82 83 /// Flag values for this instruction. 84 std::bitset<Num_Flags> flags; 85 86 /// See opClass(). 87 OpClass _opClass; 88 89 /// See numSrcRegs(). 90 int8_t _numSrcRegs; 91 92 /// See numDestRegs(). 93 int8_t _numDestRegs; 94 95 /// The following are used to track physical register usage 96 /// for machines with separate int & FP reg files. 97 //@{ 98 int8_t _numFPDestRegs; 99 int8_t _numIntDestRegs; 100 int8_t _numCCDestRegs; 101 //@} 102 103 /** To use in architectures with vector register file. */ 104 /** @{ */ 105 int8_t _numVecDestRegs; 106 int8_t _numVecElemDestRegs; 107 /** @} */ 108 109 public: 110 111 /// @name Register information. 112 /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs() and 113 /// numVecelemDestRegs() equals numDestRegs(). The former two functions 114 /// are used to track physical register usage for machines with separate 115 /// int & FP reg files, the next two is for machines with vector register 116 /// file. 117 //@{ 118 /// Number of source registers. 119 int8_t numSrcRegs() const { return _numSrcRegs; } 120 /// Number of destination registers. 121 int8_t numDestRegs() const { return _numDestRegs; } 122 /// Number of floating-point destination regs. 123 int8_t numFPDestRegs() const { return _numFPDestRegs; } 124 /// Number of integer destination regs. 125 int8_t numIntDestRegs() const { return _numIntDestRegs; } 126 /// Number of vector destination regs. 127 int8_t numVecDestRegs() const { return _numVecDestRegs; } 128 /// Number of vector element destination regs. 129 int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; } 130 /// Number of coprocesor destination regs. 131 int8_t numCCDestRegs() const { return _numCCDestRegs; } 132 //@} 133 134 /// @name Flag accessors. 135 /// These functions are used to access the values of the various 136 /// instruction property flags. See StaticInst::Flags for descriptions 137 /// of the individual flags. 138 //@{ 139 140 bool isNop() const { return flags[IsNop]; } 141 142 bool isMemRef() const { return flags[IsMemRef]; } 143 bool isLoad() const { return flags[IsLoad]; } 144 bool isStore() const { return flags[IsStore]; } 145 bool isStoreConditional() const { return flags[IsStoreConditional]; } 146 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 147 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 148 bool isPrefetch() const { return isInstPrefetch() || 149 isDataPrefetch(); } 150 151 bool isInteger() const { return flags[IsInteger]; } 152 bool isFloating() const { return flags[IsFloating]; } 153 bool isVector() const { return flags[IsVector]; } 154 bool isCC() const { return flags[IsCC]; } 155 156 bool isControl() const { return flags[IsControl]; } 157 bool isCall() const { return flags[IsCall]; } 158 bool isReturn() const { return flags[IsReturn]; } 159 bool isDirectCtrl() const { return flags[IsDirectControl]; } 160 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 161 bool isCondCtrl() const { return flags[IsCondControl]; } 162 bool isUncondCtrl() const { return flags[IsUncondControl]; } 163 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 164 165 bool isThreadSync() const { return flags[IsThreadSync]; } 166 bool isSerializing() const { return flags[IsSerializing] || 167 flags[IsSerializeBefore] || 168 flags[IsSerializeAfter]; } 169 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 170 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 171 bool isSquashAfter() const { return flags[IsSquashAfter]; } 172 bool isMemBarrier() const { return flags[IsMemBarrier]; } 173 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 174 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 175 bool isQuiesce() const { return flags[IsQuiesce]; } 176 bool isIprAccess() const { return flags[IsIprAccess]; } 177 bool isUnverifiable() const { return flags[IsUnverifiable]; } 178 bool isSyscall() const { return flags[IsSyscall]; } 179 bool isMacroop() const { return flags[IsMacroop]; } 180 bool isMicroop() const { return flags[IsMicroop]; } 181 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 182 bool isLastMicroop() const { return flags[IsLastMicroop]; } 183 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 184 //This flag doesn't do anything yet 185 bool isMicroBranch() const { return flags[IsMicroBranch]; } 186 //@} 187 188 void setFirstMicroop() { flags[IsFirstMicroop] = true; } 189 void setLastMicroop() { flags[IsLastMicroop] = true; } 190 void setDelayedCommit() { flags[IsDelayedCommit] = true; } 191 void setFlag(Flags f) { flags[f] = true; } 192 193 /// Operation class. Used to select appropriate function unit in issue. 194 OpClass opClass() const { return _opClass; } 195 196 197 /// Return logical index (architectural reg num) of i'th destination reg. 198 /// Only the entries from 0 through numDestRegs()-1 are valid. 199 const RegId& destRegIdx(int i) const { return _destRegIdx[i]; } 200 201 /// Return logical index (architectural reg num) of i'th source reg. 202 /// Only the entries from 0 through numSrcRegs()-1 are valid. 203 const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; } 204 205 /// Pointer to a statically allocated "null" instruction object. |
206 static StaticInstPtr nullStaticInstPtr; 207 |
208 /// The binary machine instruction. 209 const ExtMachInst machInst; 210 211 protected: 212 213 /// See destRegIdx(). 214 RegId _destRegIdx[MaxInstDestRegs]; 215 /// See srcRegIdx(). 216 RegId _srcRegIdx[MaxInstSrcRegs]; 217 218 /** 219 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 220 * methods. Also useful to readily identify instructions from 221 * within the debugger when #cachedDisassembly has not been 222 * initialized. 223 */ 224 const char *mnemonic; 225 226 /** 227 * String representation of disassembly (lazily evaluated via 228 * disassemble()). 229 */ 230 mutable std::string *cachedDisassembly; 231 232 /** 233 * Internal function to generate disassembly string. 234 */ 235 virtual std::string 236 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 237 238 /// Constructor. 239 /// It's important to initialize everything here to a sane 240 /// default, since the decoder generally only overrides 241 /// the fields that are meaningful for the particular 242 /// instruction. 243 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 244 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 245 _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0), 246 _numVecDestRegs(0), _numVecElemDestRegs(0), machInst(_machInst), 247 mnemonic(_mnemonic), cachedDisassembly(0) 248 { } 249 250 public: 251 virtual ~StaticInst(); 252 253 virtual Fault execute(ExecContext *xc, 254 Trace::InstRecord *traceData) const = 0; |
255 256 virtual Fault initiateAcc(ExecContext *xc, 257 Trace::InstRecord *traceData) const 258 { 259 panic("initiateAcc not defined!"); 260 } 261 262 virtual Fault completeAcc(Packet *pkt, ExecContext *xc, 263 Trace::InstRecord *traceData) const 264 { 265 panic("completeAcc not defined!"); 266 } 267 268 virtual void advancePC(TheISA::PCState &pcState) const = 0; 269 270 /** 271 * Return the microop that goes with a particular micropc. This should 272 * only be defined/used in macroops which will contain microops 273 */ 274 virtual StaticInstPtr fetchMicroop(MicroPC upc) const; 275 276 /** 277 * Return the target address for a PC-relative branch. 278 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 279 * should be true). 280 */ 281 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const; 282 283 /** 284 * Return the target address for an indirect branch (jump). The 285 * register value is read from the supplied thread context, so 286 * the result is valid only if the thread context is about to 287 * execute the branch in question. Invalid if not an indirect 288 * branch (i.e. isIndirectCtrl() should be true). 289 */ 290 virtual TheISA::PCState branchTarget(ThreadContext *tc) const; 291 292 /** 293 * Return true if the instruction is a control transfer, and if so, 294 * return the target address as well. 295 */ 296 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 297 TheISA::PCState &tgt) const; 298 299 /** 300 * Return string representation of disassembled instruction. 301 * The default version of this function will call the internal 302 * virtual generateDisassembly() function to get the string, 303 * then cache it in #cachedDisassembly. If the disassembly 304 * should not be cached, this function should be overridden directly. 305 */ 306 virtual const std::string &disassemble(Addr pc, 307 const SymbolTable *symtab = 0) const; 308 309 /** 310 * Print a separator separated list of this instruction's set flag 311 * names on the given stream. 312 */ 313 void printFlags(std::ostream &outs, const std::string &separator) const; 314 315 /// Return name of machine instruction 316 std::string getName() { return mnemonic; } 317}; 318 319#endif // __CPU_STATIC_INST_HH__ |