1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 */
31
32#ifndef __CPU_STATIC_INST_HH__
33#define __CPU_STATIC_INST_HH__
34
35#include <bitset>
36#include <string>
37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
48#include "sim/fault_fwd.hh"
49
50// forward declarations
51class Packet;
52
53struct O3CPUImpl;
54template <class Impl> class BaseO3DynInst;
55typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
56class InOrderDynInst;
57
58class CheckerCPU;
59class AtomicSimpleCPU;
60class TimingSimpleCPU;
61class InorderCPU;
|
67class SymbolTable;
68
69namespace Trace {
70 class InstRecord;
71}
72
73/**
74 * Base, ISA-independent static instruction class.
75 *
76 * The main component of this class is the vector of flags and the
77 * associated methods for reading them. Any object that can rely
78 * solely on these flags can process instructions without being
79 * recompiled for multiple ISAs.
80 */
81class StaticInst : public RefCounted, public StaticInstFlags
82{
83 public:
84 /// Binary extended machine instruction type.
85 typedef TheISA::ExtMachInst ExtMachInst;
86 /// Logical register index type.
87 typedef TheISA::RegIndex RegIndex;
88
89 enum {
90 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
91 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
92 };
93
94 protected:
95
96 /// Flag values for this instruction.
97 std::bitset<Num_Flags> flags;
98
99 /// See opClass().
100 OpClass _opClass;
101
102 /// See numSrcRegs().
103 int8_t _numSrcRegs;
104
105 /// See numDestRegs().
106 int8_t _numDestRegs;
107
108 /// The following are used to track physical register usage
109 /// for machines with separate int & FP reg files.
110 //@{
111 int8_t _numFPDestRegs;
112 int8_t _numIntDestRegs;
113 int8_t _numCCDestRegs;
114 //@}
115
116 public:
117
118 /// @name Register information.
119 /// The sum of numFPDestRegs() and numIntDestRegs() equals
120 /// numDestRegs(). The former two functions are used to track
121 /// physical register usage for machines with separate int & FP
122 /// reg files.
123 //@{
124 /// Number of source registers.
125 int8_t numSrcRegs() const { return _numSrcRegs; }
126 /// Number of destination registers.
127 int8_t numDestRegs() const { return _numDestRegs; }
128 /// Number of floating-point destination regs.
129 int8_t numFPDestRegs() const { return _numFPDestRegs; }
130 /// Number of integer destination regs.
131 int8_t numIntDestRegs() const { return _numIntDestRegs; }
132 //@}
133
134 /// @name Flag accessors.
135 /// These functions are used to access the values of the various
136 /// instruction property flags. See StaticInst::Flags for descriptions
137 /// of the individual flags.
138 //@{
139
140 bool isNop() const { return flags[IsNop]; }
141
142 bool isMemRef() const { return flags[IsMemRef]; }
143 bool isLoad() const { return flags[IsLoad]; }
144 bool isStore() const { return flags[IsStore]; }
145 bool isStoreConditional() const { return flags[IsStoreConditional]; }
146 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
147 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
148 bool isPrefetch() const { return isInstPrefetch() ||
149 isDataPrefetch(); }
150
151 bool isInteger() const { return flags[IsInteger]; }
152 bool isFloating() const { return flags[IsFloating]; }
153 bool isCC() const { return flags[IsCC]; }
154
155 bool isControl() const { return flags[IsControl]; }
156 bool isCall() const { return flags[IsCall]; }
157 bool isReturn() const { return flags[IsReturn]; }
158 bool isDirectCtrl() const { return flags[IsDirectControl]; }
159 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
160 bool isCondCtrl() const { return flags[IsCondControl]; }
161 bool isUncondCtrl() const { return flags[IsUncondControl]; }
162 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
163
164 bool isThreadSync() const { return flags[IsThreadSync]; }
165 bool isSerializing() const { return flags[IsSerializing] ||
166 flags[IsSerializeBefore] ||
167 flags[IsSerializeAfter]; }
168 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
169 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
170 bool isSquashAfter() const { return flags[IsSquashAfter]; }
171 bool isMemBarrier() const { return flags[IsMemBarrier]; }
172 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
173 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
174 bool isQuiesce() const { return flags[IsQuiesce]; }
175 bool isIprAccess() const { return flags[IsIprAccess]; }
176 bool isUnverifiable() const { return flags[IsUnverifiable]; }
177 bool isSyscall() const { return flags[IsSyscall]; }
178 bool isMacroop() const { return flags[IsMacroop]; }
179 bool isMicroop() const { return flags[IsMicroop]; }
180 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
181 bool isLastMicroop() const { return flags[IsLastMicroop]; }
182 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
183 //This flag doesn't do anything yet
184 bool isMicroBranch() const { return flags[IsMicroBranch]; }
185 //@}
186
187 void setLastMicroop() { flags[IsLastMicroop] = true; }
188 void setDelayedCommit() { flags[IsDelayedCommit] = true; }
189 void setFlag(Flags f) { flags[f] = true; }
190
191 /// Operation class. Used to select appropriate function unit in issue.
192 OpClass opClass() const { return _opClass; }
193
194
195 /// Return logical index (architectural reg num) of i'th destination reg.
196 /// Only the entries from 0 through numDestRegs()-1 are valid.
197 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
198
199 /// Return logical index (architectural reg num) of i'th source reg.
200 /// Only the entries from 0 through numSrcRegs()-1 are valid.
201 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
202
203 /// Pointer to a statically allocated "null" instruction object.
204 /// Used to give eaCompInst() and memAccInst() something to return
205 /// when called on non-memory instructions.
206 static StaticInstPtr nullStaticInstPtr;
207
208 /**
209 * Memory references only: returns "fake" instruction representing
210 * the effective address part of the memory operation. Used to
211 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
212 * just the EA computation.
213 */
214 virtual const
215 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
216
217 /**
218 * Memory references only: returns "fake" instruction representing
219 * the memory access part of the memory operation. Used to
220 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
221 * just the memory access (not the EA computation).
222 */
223 virtual const
224 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
225
226 /// The binary machine instruction.
227 const ExtMachInst machInst;
228
229 protected:
230
231 /// See destRegIdx().
232 RegIndex _destRegIdx[MaxInstDestRegs];
233 /// See srcRegIdx().
234 RegIndex _srcRegIdx[MaxInstSrcRegs];
235
236 /**
237 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
238 * methods. Also useful to readily identify instructions from
239 * within the debugger when #cachedDisassembly has not been
240 * initialized.
241 */
242 const char *mnemonic;
243
244 /**
245 * String representation of disassembly (lazily evaluated via
246 * disassemble()).
247 */
248 mutable std::string *cachedDisassembly;
249
250 /**
251 * Internal function to generate disassembly string.
252 */
253 virtual std::string
254 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
255
256 /// Constructor.
257 /// It's important to initialize everything here to a sane
258 /// default, since the decoder generally only overrides
259 /// the fields that are meaningful for the particular
260 /// instruction.
261 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
262 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
263 _numFPDestRegs(0), _numIntDestRegs(0),
264 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
265 { }
266
267 public:
268 virtual ~StaticInst();
269
270/**
271 * The execute() signatures are auto-generated by scons based on the
272 * set of CPU models we are compiling in today.
273 */
274#include "cpu/static_inst_exec_sigs.hh"
275
276 virtual void advancePC(TheISA::PCState &pcState) const = 0;
277
278 /**
279 * Return the microop that goes with a particular micropc. This should
280 * only be defined/used in macroops which will contain microops
281 */
282 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
283
284 /**
285 * Return the target address for a PC-relative branch.
286 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
287 * should be true).
288 */
289 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
290
291 /**
292 * Return the target address for an indirect branch (jump). The
293 * register value is read from the supplied thread context, so
294 * the result is valid only if the thread context is about to
295 * execute the branch in question. Invalid if not an indirect
296 * branch (i.e. isIndirectCtrl() should be true).
297 */
298 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
299
300 /**
301 * Return true if the instruction is a control transfer, and if so,
302 * return the target address as well.
303 */
304 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
305 TheISA::PCState &tgt) const;
306
307 /**
308 * Return string representation of disassembled instruction.
309 * The default version of this function will call the internal
310 * virtual generateDisassembly() function to get the string,
311 * then cache it in #cachedDisassembly. If the disassembly
312 * should not be cached, this function should be overridden directly.
313 */
314 virtual const std::string &disassemble(Addr pc,
315 const SymbolTable *symtab = 0) const;
316
317 /**
318 * Print a separator separated list of this instruction's set flag
319 * names on the given stream.
320 */
321 void printFlags(std::ostream &outs, const std::string &separator) const;
322
323 /// Return name of machine instruction
324 std::string getName() { return mnemonic; }
325};
326
327#endif // __CPU_STATIC_INST_HH__
|