1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 189 unchanged lines hidden (view full) --- 198 /// Only the entries from 0 through numDestRegs()-1 are valid. 199 const RegId& destRegIdx(int i) const { return _destRegIdx[i]; } 200 201 /// Return logical index (architectural reg num) of i'th source reg. 202 /// Only the entries from 0 through numSrcRegs()-1 are valid. 203 const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; } 204 205 /// Pointer to a statically allocated "null" instruction object. |
206 static StaticInstPtr nullStaticInstPtr; 207 |
208 /// The binary machine instruction. 209 const ExtMachInst machInst; 210 211 protected: 212 213 /// See destRegIdx(). 214 RegId _destRegIdx[MaxInstDestRegs]; 215 /// See srcRegIdx(). --- 31 unchanged lines hidden (view full) --- 247 mnemonic(_mnemonic), cachedDisassembly(0) 248 { } 249 250 public: 251 virtual ~StaticInst(); 252 253 virtual Fault execute(ExecContext *xc, 254 Trace::InstRecord *traceData) const = 0; |
255 256 virtual Fault initiateAcc(ExecContext *xc, 257 Trace::InstRecord *traceData) const 258 { 259 panic("initiateAcc not defined!"); 260 } 261 262 virtual Fault completeAcc(Packet *pkt, ExecContext *xc, --- 57 unchanged lines hidden --- |