1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 36 unchanged lines hidden (view full) --- 45#include "cpu/static_inst_fwd.hh" 46#include "cpu/thread_context.hh" 47#include "enums/StaticInstFlags.hh" 48#include "sim/fault_fwd.hh" 49 50// forward declarations 51class Packet; 52 |
53class ExecContext; |
54 |
55class SymbolTable; 56 57namespace Trace { 58 class InstRecord; 59} 60 61/** 62 * Base, ISA-independent static instruction class. --- 187 unchanged lines hidden (view full) --- 250 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 251 _numFPDestRegs(0), _numIntDestRegs(0), 252 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 253 { } 254 255 public: 256 virtual ~StaticInst(); 257 |
258 virtual Fault execute(ExecContext *xc, 259 Trace::InstRecord *traceData) const = 0; 260 virtual Fault eaComp(ExecContext *xc, 261 Trace::InstRecord *traceData) const 262 { 263 panic("eaComp not defined!"); 264 } |
265 |
266 virtual Fault initiateAcc(ExecContext *xc, 267 Trace::InstRecord *traceData) const 268 { 269 panic("initiateAcc not defined!"); 270 } 271 272 virtual Fault completeAcc(Packet *pkt, ExecContext *xc, 273 Trace::InstRecord *traceData) const 274 { 275 panic("completeAcc not defined!"); 276 } 277 |
278 virtual void advancePC(TheISA::PCState &pcState) const = 0; 279 280 /** 281 * Return the microop that goes with a particular micropc. This should 282 * only be defined/used in macroops which will contain microops 283 */ 284 virtual StaticInstPtr fetchMicroop(MicroPC upc) const; 285 --- 44 unchanged lines hidden --- |