1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
|
| 3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
|
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/registers.hh"
38#include "arch/types.hh"
39#include "base/misc.hh"
40#include "base/refcnt.hh"
41#include "base/types.hh"
42#include "config/the_isa.hh"
43#include "cpu/op_class.hh"
44#include "cpu/static_inst_fwd.hh"
45#include "cpu/thread_context.hh"
46#include "sim/fault_fwd.hh"
47
48// forward declarations
49class Packet;
50
51struct O3CPUImpl;
52template <class Impl> class BaseO3DynInst;
53typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
54class InOrderDynInst;
55
56class CheckerCPU;
57class AtomicSimpleCPU;
58class TimingSimpleCPU;
59class InorderCPU;
60class SymbolTable;
61
62namespace Trace {
63 class InstRecord;
64}
65
66/**
67 * Base, ISA-independent static instruction class.
68 *
69 * The main component of this class is the vector of flags and the
70 * associated methods for reading them. Any object that can rely
71 * solely on these flags can process instructions without being
72 * recompiled for multiple ISAs.
73 */
74class StaticInst : public RefCounted
75{
76 public:
77 /// Binary extended machine instruction type.
78 typedef TheISA::ExtMachInst ExtMachInst;
79 /// Logical register index type.
80 typedef TheISA::RegIndex RegIndex;
81
82 enum {
83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
85 };
86
87 /// Set of boolean static instruction properties.
88 ///
89 /// Notes:
90 /// - The IsInteger and IsFloating flags are based on the class of
91 /// registers accessed by the instruction. Although most
92 /// instructions will have exactly one of these two flags set, it
93 /// is possible for an instruction to have neither (e.g., direct
94 /// unconditional branches, memory barriers) or both (e.g., an
95 /// FP/int conversion).
96 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
97 /// will be set.
98 /// - If IsControl is set, then exactly one of IsDirectControl or
99 /// IsIndirect Control will be set, and exactly one of
100 /// IsCondControl or IsUncondControl will be set.
101 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
102 /// implemented as flags since in the current model there's no
103 /// other way for instructions to inject behavior into the
104 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
105 /// model we should be able to get rid of these flags and
106 /// implement this behavior via the execute() methods.
107 ///
108 enum Flags {
109 IsNop, ///< Is a no-op (no effect at all).
110
111 IsInteger, ///< References integer regs.
112 IsFloating, ///< References FP regs.
| 4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 */
31
32#ifndef __CPU_STATIC_INST_HH__
33#define __CPU_STATIC_INST_HH__
34
35#include <bitset>
36#include <string>
37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "sim/fault_fwd.hh"
48
49// forward declarations
50class Packet;
51
52struct O3CPUImpl;
53template <class Impl> class BaseO3DynInst;
54typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
55class InOrderDynInst;
56
57class CheckerCPU;
58class AtomicSimpleCPU;
59class TimingSimpleCPU;
60class InorderCPU;
61class SymbolTable;
62
63namespace Trace {
64 class InstRecord;
65}
66
67/**
68 * Base, ISA-independent static instruction class.
69 *
70 * The main component of this class is the vector of flags and the
71 * associated methods for reading them. Any object that can rely
72 * solely on these flags can process instructions without being
73 * recompiled for multiple ISAs.
74 */
75class StaticInst : public RefCounted
76{
77 public:
78 /// Binary extended machine instruction type.
79 typedef TheISA::ExtMachInst ExtMachInst;
80 /// Logical register index type.
81 typedef TheISA::RegIndex RegIndex;
82
83 enum {
84 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
85 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
86 };
87
88 /// Set of boolean static instruction properties.
89 ///
90 /// Notes:
91 /// - The IsInteger and IsFloating flags are based on the class of
92 /// registers accessed by the instruction. Although most
93 /// instructions will have exactly one of these two flags set, it
94 /// is possible for an instruction to have neither (e.g., direct
95 /// unconditional branches, memory barriers) or both (e.g., an
96 /// FP/int conversion).
97 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
98 /// will be set.
99 /// - If IsControl is set, then exactly one of IsDirectControl or
100 /// IsIndirect Control will be set, and exactly one of
101 /// IsCondControl or IsUncondControl will be set.
102 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
103 /// implemented as flags since in the current model there's no
104 /// other way for instructions to inject behavior into the
105 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
106 /// model we should be able to get rid of these flags and
107 /// implement this behavior via the execute() methods.
108 ///
109 enum Flags {
110 IsNop, ///< Is a no-op (no effect at all).
111
112 IsInteger, ///< References integer regs.
113 IsFloating, ///< References FP regs.
|
| 114 IsCC, ///< References CC regs.
|
113
114 IsMemRef, ///< References memory (load, store, or prefetch).
115 IsLoad, ///< Reads from memory (load or prefetch).
116 IsStore, ///< Writes to memory.
117 IsStoreConditional, ///< Store conditional instruction.
118 IsIndexed, ///< Accesses memory with an indexed address computation
119 IsInstPrefetch, ///< Instruction-cache prefetch.
120 IsDataPrefetch, ///< Data-cache prefetch.
121
122 IsControl, ///< Control transfer instruction.
123 IsDirectControl, ///< PC relative control transfer.
124 IsIndirectControl, ///< Register indirect control transfer.
125 IsCondControl, ///< Conditional control transfer.
126 IsUncondControl, ///< Unconditional control transfer.
127 IsCall, ///< Subroutine call.
128 IsReturn, ///< Subroutine return.
129
130 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
131
132 IsThreadSync, ///< Thread synchronization operation.
133
134 IsSerializing, ///< Serializes pipeline: won't execute until all
135 /// older instructions have committed.
136 IsSerializeBefore,
137 IsSerializeAfter,
138 IsMemBarrier, ///< Is a memory barrier
139 IsWriteBarrier, ///< Is a write barrier
140 IsReadBarrier, ///< Is a read barrier
141 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
142
143 IsNonSpeculative, ///< Should not be executed speculatively
144 IsQuiesce, ///< Is a quiesce instruction
145
146 IsIprAccess, ///< Accesses IPRs
147 IsUnverifiable, ///< Can't be verified by a checker
148
149 IsSyscall, ///< Causes a system call to be emulated in syscall
150 /// emulation mode.
151
152 //Flags for microcode
153 IsMacroop, ///< Is a macroop containing microops
154 IsMicroop, ///< Is a microop
155 IsDelayedCommit, ///< This microop doesn't commit right away
156 IsLastMicroop, ///< This microop ends a microop sequence
157 IsFirstMicroop, ///< This microop begins a microop sequence
158 //This flag doesn't do anything yet
159 IsMicroBranch, ///< This microop branches within the microcode for a macroop
160 IsDspOp,
161 IsSquashAfter, ///< Squash all uncommitted state after executed
162 NumFlags
163 };
164
165 protected:
166
167 /// Flag values for this instruction.
168 std::bitset<NumFlags> flags;
169
170 /// See opClass().
171 OpClass _opClass;
172
173 /// See numSrcRegs().
174 int8_t _numSrcRegs;
175
176 /// See numDestRegs().
177 int8_t _numDestRegs;
178
179 /// The following are used to track physical register usage
180 /// for machines with separate int & FP reg files.
181 //@{
182 int8_t _numFPDestRegs;
183 int8_t _numIntDestRegs;
| 115
116 IsMemRef, ///< References memory (load, store, or prefetch).
117 IsLoad, ///< Reads from memory (load or prefetch).
118 IsStore, ///< Writes to memory.
119 IsStoreConditional, ///< Store conditional instruction.
120 IsIndexed, ///< Accesses memory with an indexed address computation
121 IsInstPrefetch, ///< Instruction-cache prefetch.
122 IsDataPrefetch, ///< Data-cache prefetch.
123
124 IsControl, ///< Control transfer instruction.
125 IsDirectControl, ///< PC relative control transfer.
126 IsIndirectControl, ///< Register indirect control transfer.
127 IsCondControl, ///< Conditional control transfer.
128 IsUncondControl, ///< Unconditional control transfer.
129 IsCall, ///< Subroutine call.
130 IsReturn, ///< Subroutine return.
131
132 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
133
134 IsThreadSync, ///< Thread synchronization operation.
135
136 IsSerializing, ///< Serializes pipeline: won't execute until all
137 /// older instructions have committed.
138 IsSerializeBefore,
139 IsSerializeAfter,
140 IsMemBarrier, ///< Is a memory barrier
141 IsWriteBarrier, ///< Is a write barrier
142 IsReadBarrier, ///< Is a read barrier
143 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
144
145 IsNonSpeculative, ///< Should not be executed speculatively
146 IsQuiesce, ///< Is a quiesce instruction
147
148 IsIprAccess, ///< Accesses IPRs
149 IsUnverifiable, ///< Can't be verified by a checker
150
151 IsSyscall, ///< Causes a system call to be emulated in syscall
152 /// emulation mode.
153
154 //Flags for microcode
155 IsMacroop, ///< Is a macroop containing microops
156 IsMicroop, ///< Is a microop
157 IsDelayedCommit, ///< This microop doesn't commit right away
158 IsLastMicroop, ///< This microop ends a microop sequence
159 IsFirstMicroop, ///< This microop begins a microop sequence
160 //This flag doesn't do anything yet
161 IsMicroBranch, ///< This microop branches within the microcode for a macroop
162 IsDspOp,
163 IsSquashAfter, ///< Squash all uncommitted state after executed
164 NumFlags
165 };
166
167 protected:
168
169 /// Flag values for this instruction.
170 std::bitset<NumFlags> flags;
171
172 /// See opClass().
173 OpClass _opClass;
174
175 /// See numSrcRegs().
176 int8_t _numSrcRegs;
177
178 /// See numDestRegs().
179 int8_t _numDestRegs;
180
181 /// The following are used to track physical register usage
182 /// for machines with separate int & FP reg files.
183 //@{
184 int8_t _numFPDestRegs;
185 int8_t _numIntDestRegs;
|
| 186 int8_t _numCCDestRegs;
|
184 //@}
185
186 public:
187
188 /// @name Register information.
189 /// The sum of numFPDestRegs() and numIntDestRegs() equals
190 /// numDestRegs(). The former two functions are used to track
191 /// physical register usage for machines with separate int & FP
192 /// reg files.
193 //@{
194 /// Number of source registers.
195 int8_t numSrcRegs() const { return _numSrcRegs; }
196 /// Number of destination registers.
197 int8_t numDestRegs() const { return _numDestRegs; }
198 /// Number of floating-point destination regs.
199 int8_t numFPDestRegs() const { return _numFPDestRegs; }
200 /// Number of integer destination regs.
201 int8_t numIntDestRegs() const { return _numIntDestRegs; }
202 //@}
203
204 /// @name Flag accessors.
205 /// These functions are used to access the values of the various
206 /// instruction property flags. See StaticInst::Flags for descriptions
207 /// of the individual flags.
208 //@{
209
210 bool isNop() const { return flags[IsNop]; }
211
212 bool isMemRef() const { return flags[IsMemRef]; }
213 bool isLoad() const { return flags[IsLoad]; }
214 bool isStore() const { return flags[IsStore]; }
215 bool isStoreConditional() const { return flags[IsStoreConditional]; }
216 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
217 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
218 bool isPrefetch() const { return isInstPrefetch() ||
219 isDataPrefetch(); }
220
221 bool isInteger() const { return flags[IsInteger]; }
222 bool isFloating() const { return flags[IsFloating]; }
| 187 //@}
188
189 public:
190
191 /// @name Register information.
192 /// The sum of numFPDestRegs() and numIntDestRegs() equals
193 /// numDestRegs(). The former two functions are used to track
194 /// physical register usage for machines with separate int & FP
195 /// reg files.
196 //@{
197 /// Number of source registers.
198 int8_t numSrcRegs() const { return _numSrcRegs; }
199 /// Number of destination registers.
200 int8_t numDestRegs() const { return _numDestRegs; }
201 /// Number of floating-point destination regs.
202 int8_t numFPDestRegs() const { return _numFPDestRegs; }
203 /// Number of integer destination regs.
204 int8_t numIntDestRegs() const { return _numIntDestRegs; }
205 //@}
206
207 /// @name Flag accessors.
208 /// These functions are used to access the values of the various
209 /// instruction property flags. See StaticInst::Flags for descriptions
210 /// of the individual flags.
211 //@{
212
213 bool isNop() const { return flags[IsNop]; }
214
215 bool isMemRef() const { return flags[IsMemRef]; }
216 bool isLoad() const { return flags[IsLoad]; }
217 bool isStore() const { return flags[IsStore]; }
218 bool isStoreConditional() const { return flags[IsStoreConditional]; }
219 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
220 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
221 bool isPrefetch() const { return isInstPrefetch() ||
222 isDataPrefetch(); }
223
224 bool isInteger() const { return flags[IsInteger]; }
225 bool isFloating() const { return flags[IsFloating]; }
|
| 226 bool isCC() const { return flags[IsCC]; }
|
223
224 bool isControl() const { return flags[IsControl]; }
225 bool isCall() const { return flags[IsCall]; }
226 bool isReturn() const { return flags[IsReturn]; }
227 bool isDirectCtrl() const { return flags[IsDirectControl]; }
228 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
229 bool isCondCtrl() const { return flags[IsCondControl]; }
230 bool isUncondCtrl() const { return flags[IsUncondControl]; }
231 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
232
233 bool isThreadSync() const { return flags[IsThreadSync]; }
234 bool isSerializing() const { return flags[IsSerializing] ||
235 flags[IsSerializeBefore] ||
236 flags[IsSerializeAfter]; }
237 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
238 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
239 bool isSquashAfter() const { return flags[IsSquashAfter]; }
240 bool isMemBarrier() const { return flags[IsMemBarrier]; }
241 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
242 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
243 bool isQuiesce() const { return flags[IsQuiesce]; }
244 bool isIprAccess() const { return flags[IsIprAccess]; }
245 bool isUnverifiable() const { return flags[IsUnverifiable]; }
246 bool isSyscall() const { return flags[IsSyscall]; }
247 bool isMacroop() const { return flags[IsMacroop]; }
248 bool isMicroop() const { return flags[IsMicroop]; }
249 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
250 bool isLastMicroop() const { return flags[IsLastMicroop]; }
251 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
252 //This flag doesn't do anything yet
253 bool isMicroBranch() const { return flags[IsMicroBranch]; }
254 //@}
255
256 void setLastMicroop() { flags[IsLastMicroop] = true; }
257 void setDelayedCommit() { flags[IsDelayedCommit] = true; }
258 void setFlag(Flags f) { flags[f] = true; }
259
260 /// Operation class. Used to select appropriate function unit in issue.
261 OpClass opClass() const { return _opClass; }
262
263
264 /// Return logical index (architectural reg num) of i'th destination reg.
265 /// Only the entries from 0 through numDestRegs()-1 are valid.
266 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
267
268 /// Return logical index (architectural reg num) of i'th source reg.
269 /// Only the entries from 0 through numSrcRegs()-1 are valid.
270 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
271
272 /// Pointer to a statically allocated "null" instruction object.
273 /// Used to give eaCompInst() and memAccInst() something to return
274 /// when called on non-memory instructions.
275 static StaticInstPtr nullStaticInstPtr;
276
277 /**
278 * Memory references only: returns "fake" instruction representing
279 * the effective address part of the memory operation. Used to
280 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
281 * just the EA computation.
282 */
283 virtual const
284 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
285
286 /**
287 * Memory references only: returns "fake" instruction representing
288 * the memory access part of the memory operation. Used to
289 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
290 * just the memory access (not the EA computation).
291 */
292 virtual const
293 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
294
295 /// The binary machine instruction.
296 const ExtMachInst machInst;
297
298 protected:
299
300 /// See destRegIdx().
301 RegIndex _destRegIdx[MaxInstDestRegs];
302 /// See srcRegIdx().
303 RegIndex _srcRegIdx[MaxInstSrcRegs];
304
305 /**
306 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
307 * methods. Also useful to readily identify instructions from
308 * within the debugger when #cachedDisassembly has not been
309 * initialized.
310 */
311 const char *mnemonic;
312
313 /**
314 * String representation of disassembly (lazily evaluated via
315 * disassemble()).
316 */
317 mutable std::string *cachedDisassembly;
318
319 /**
320 * Internal function to generate disassembly string.
321 */
322 virtual std::string
323 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
324
325 /// Constructor.
326 /// It's important to initialize everything here to a sane
327 /// default, since the decoder generally only overrides
328 /// the fields that are meaningful for the particular
329 /// instruction.
330 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
331 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
332 _numFPDestRegs(0), _numIntDestRegs(0),
333 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
334 { }
335
336 public:
337 virtual ~StaticInst();
338
339/**
340 * The execute() signatures are auto-generated by scons based on the
341 * set of CPU models we are compiling in today.
342 */
343#include "cpu/static_inst_exec_sigs.hh"
344
345 virtual void advancePC(TheISA::PCState &pcState) const = 0;
346
347 /**
348 * Return the microop that goes with a particular micropc. This should
349 * only be defined/used in macroops which will contain microops
350 */
351 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
352
353 /**
354 * Return the target address for a PC-relative branch.
355 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
356 * should be true).
357 */
358 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
359
360 /**
361 * Return the target address for an indirect branch (jump). The
362 * register value is read from the supplied thread context, so
363 * the result is valid only if the thread context is about to
364 * execute the branch in question. Invalid if not an indirect
365 * branch (i.e. isIndirectCtrl() should be true).
366 */
367 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
368
369 /**
370 * Return true if the instruction is a control transfer, and if so,
371 * return the target address as well.
372 */
373 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
374 TheISA::PCState &tgt) const;
375
376 /**
377 * Return string representation of disassembled instruction.
378 * The default version of this function will call the internal
379 * virtual generateDisassembly() function to get the string,
380 * then cache it in #cachedDisassembly. If the disassembly
381 * should not be cached, this function should be overridden directly.
382 */
383 virtual const std::string &disassemble(Addr pc,
384 const SymbolTable *symtab = 0) const;
385
386 /// Return name of machine instruction
387 std::string getName() { return mnemonic; }
388};
389
390#endif // __CPU_STATIC_INST_HH__
| 227
228 bool isControl() const { return flags[IsControl]; }
229 bool isCall() const { return flags[IsCall]; }
230 bool isReturn() const { return flags[IsReturn]; }
231 bool isDirectCtrl() const { return flags[IsDirectControl]; }
232 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
233 bool isCondCtrl() const { return flags[IsCondControl]; }
234 bool isUncondCtrl() const { return flags[IsUncondControl]; }
235 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
236
237 bool isThreadSync() const { return flags[IsThreadSync]; }
238 bool isSerializing() const { return flags[IsSerializing] ||
239 flags[IsSerializeBefore] ||
240 flags[IsSerializeAfter]; }
241 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
242 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
243 bool isSquashAfter() const { return flags[IsSquashAfter]; }
244 bool isMemBarrier() const { return flags[IsMemBarrier]; }
245 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
246 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
247 bool isQuiesce() const { return flags[IsQuiesce]; }
248 bool isIprAccess() const { return flags[IsIprAccess]; }
249 bool isUnverifiable() const { return flags[IsUnverifiable]; }
250 bool isSyscall() const { return flags[IsSyscall]; }
251 bool isMacroop() const { return flags[IsMacroop]; }
252 bool isMicroop() const { return flags[IsMicroop]; }
253 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
254 bool isLastMicroop() const { return flags[IsLastMicroop]; }
255 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
256 //This flag doesn't do anything yet
257 bool isMicroBranch() const { return flags[IsMicroBranch]; }
258 //@}
259
260 void setLastMicroop() { flags[IsLastMicroop] = true; }
261 void setDelayedCommit() { flags[IsDelayedCommit] = true; }
262 void setFlag(Flags f) { flags[f] = true; }
263
264 /// Operation class. Used to select appropriate function unit in issue.
265 OpClass opClass() const { return _opClass; }
266
267
268 /// Return logical index (architectural reg num) of i'th destination reg.
269 /// Only the entries from 0 through numDestRegs()-1 are valid.
270 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
271
272 /// Return logical index (architectural reg num) of i'th source reg.
273 /// Only the entries from 0 through numSrcRegs()-1 are valid.
274 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
275
276 /// Pointer to a statically allocated "null" instruction object.
277 /// Used to give eaCompInst() and memAccInst() something to return
278 /// when called on non-memory instructions.
279 static StaticInstPtr nullStaticInstPtr;
280
281 /**
282 * Memory references only: returns "fake" instruction representing
283 * the effective address part of the memory operation. Used to
284 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
285 * just the EA computation.
286 */
287 virtual const
288 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
289
290 /**
291 * Memory references only: returns "fake" instruction representing
292 * the memory access part of the memory operation. Used to
293 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
294 * just the memory access (not the EA computation).
295 */
296 virtual const
297 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
298
299 /// The binary machine instruction.
300 const ExtMachInst machInst;
301
302 protected:
303
304 /// See destRegIdx().
305 RegIndex _destRegIdx[MaxInstDestRegs];
306 /// See srcRegIdx().
307 RegIndex _srcRegIdx[MaxInstSrcRegs];
308
309 /**
310 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
311 * methods. Also useful to readily identify instructions from
312 * within the debugger when #cachedDisassembly has not been
313 * initialized.
314 */
315 const char *mnemonic;
316
317 /**
318 * String representation of disassembly (lazily evaluated via
319 * disassemble()).
320 */
321 mutable std::string *cachedDisassembly;
322
323 /**
324 * Internal function to generate disassembly string.
325 */
326 virtual std::string
327 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
328
329 /// Constructor.
330 /// It's important to initialize everything here to a sane
331 /// default, since the decoder generally only overrides
332 /// the fields that are meaningful for the particular
333 /// instruction.
334 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
335 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
336 _numFPDestRegs(0), _numIntDestRegs(0),
337 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
338 { }
339
340 public:
341 virtual ~StaticInst();
342
343/**
344 * The execute() signatures are auto-generated by scons based on the
345 * set of CPU models we are compiling in today.
346 */
347#include "cpu/static_inst_exec_sigs.hh"
348
349 virtual void advancePC(TheISA::PCState &pcState) const = 0;
350
351 /**
352 * Return the microop that goes with a particular micropc. This should
353 * only be defined/used in macroops which will contain microops
354 */
355 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
356
357 /**
358 * Return the target address for a PC-relative branch.
359 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
360 * should be true).
361 */
362 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
363
364 /**
365 * Return the target address for an indirect branch (jump). The
366 * register value is read from the supplied thread context, so
367 * the result is valid only if the thread context is about to
368 * execute the branch in question. Invalid if not an indirect
369 * branch (i.e. isIndirectCtrl() should be true).
370 */
371 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
372
373 /**
374 * Return true if the instruction is a control transfer, and if so,
375 * return the target address as well.
376 */
377 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
378 TheISA::PCState &tgt) const;
379
380 /**
381 * Return string representation of disassembled instruction.
382 * The default version of this function will call the internal
383 * virtual generateDisassembly() function to get the string,
384 * then cache it in #cachedDisassembly. If the disassembly
385 * should not be cached, this function should be overridden directly.
386 */
387 virtual const std::string &disassemble(Addr pc,
388 const SymbolTable *symtab = 0) const;
389
390 /// Return name of machine instruction
391 std::string getName() { return mnemonic; }
392};
393
394#endif // __CPU_STATIC_INST_HH__
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