static_inst.hh (8229:78bf55f23338) static_inst.hh (8541:27aaee8ec7cc)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "arch/registers.hh"
39#include "arch/types.hh"
37#include "arch/registers.hh"
38#include "arch/types.hh"
40#include "base/hashmap.hh"
41#include "base/misc.hh"
42#include "base/refcnt.hh"
43#include "base/types.hh"
44#include "config/the_isa.hh"
45#include "cpu/op_class.hh"
46#include "sim/fault_fwd.hh"
47
48// forward declarations
49struct AlphaSimpleImpl;
50struct OzoneImpl;
51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56class O3CPUImpl;
57template <class Impl> class BaseO3DynInst;
58typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
59template <class Impl> class OzoneDynInst;
60class InOrderDynInst;
61
62class CheckerCPU;
63class FastCPU;
64class AtomicSimpleCPU;
65class TimingSimpleCPU;
66class InorderCPU;
67class SymbolTable;
39#include "base/misc.hh"
40#include "base/refcnt.hh"
41#include "base/types.hh"
42#include "config/the_isa.hh"
43#include "cpu/op_class.hh"
44#include "sim/fault_fwd.hh"
45
46// forward declarations
47struct AlphaSimpleImpl;
48struct OzoneImpl;
49struct SimpleImpl;
50class ThreadContext;
51class DynInst;
52class Packet;
53
54class O3CPUImpl;
55template <class Impl> class BaseO3DynInst;
56typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
57template <class Impl> class OzoneDynInst;
58class InOrderDynInst;
59
60class CheckerCPU;
61class FastCPU;
62class AtomicSimpleCPU;
63class TimingSimpleCPU;
64class InorderCPU;
65class SymbolTable;
68class AddrDecodePage;
69
70namespace Trace {
71 class InstRecord;
72}
73
74/**
75 * Base, ISA-independent static instruction class.
76 *
77 * The main component of this class is the vector of flags and the
78 * associated methods for reading them. Any object that can rely
79 * solely on these flags can process instructions without being
80 * recompiled for multiple ISAs.
81 */
82class StaticInstBase : public RefCounted
83{
84 public:
85
86 /// Set of boolean static instruction properties.
87 ///
88 /// Notes:
89 /// - The IsInteger and IsFloating flags are based on the class of
90 /// registers accessed by the instruction. Although most
91 /// instructions will have exactly one of these two flags set, it
92 /// is possible for an instruction to have neither (e.g., direct
93 /// unconditional branches, memory barriers) or both (e.g., an
94 /// FP/int conversion).
95 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
96 /// will be set.
97 /// - If IsControl is set, then exactly one of IsDirectControl or
98 /// IsIndirect Control will be set, and exactly one of
99 /// IsCondControl or IsUncondControl will be set.
100 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
101 /// implemented as flags since in the current model there's no
102 /// other way for instructions to inject behavior into the
103 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
104 /// model we should be able to get rid of these flags and
105 /// implement this behavior via the execute() methods.
106 ///
107 enum Flags {
108 IsNop, ///< Is a no-op (no effect at all).
109
110 IsInteger, ///< References integer regs.
111 IsFloating, ///< References FP regs.
112
113 IsMemRef, ///< References memory (load, store, or prefetch).
114 IsLoad, ///< Reads from memory (load or prefetch).
115 IsStore, ///< Writes to memory.
116 IsStoreConditional, ///< Store conditional instruction.
117 IsIndexed, ///< Accesses memory with an indexed address computation
118 IsInstPrefetch, ///< Instruction-cache prefetch.
119 IsDataPrefetch, ///< Data-cache prefetch.
120
121 IsControl, ///< Control transfer instruction.
122 IsDirectControl, ///< PC relative control transfer.
123 IsIndirectControl, ///< Register indirect control transfer.
124 IsCondControl, ///< Conditional control transfer.
125 IsUncondControl, ///< Unconditional control transfer.
126 IsCall, ///< Subroutine call.
127 IsReturn, ///< Subroutine return.
128
129 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
130
131 IsThreadSync, ///< Thread synchronization operation.
132
133 IsSerializing, ///< Serializes pipeline: won't execute until all
134 /// older instructions have committed.
135 IsSerializeBefore,
136 IsSerializeAfter,
137 IsMemBarrier, ///< Is a memory barrier
138 IsWriteBarrier, ///< Is a write barrier
139 IsReadBarrier, ///< Is a read barrier
140 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
141
142 IsNonSpeculative, ///< Should not be executed speculatively
143 IsQuiesce, ///< Is a quiesce instruction
144
145 IsIprAccess, ///< Accesses IPRs
146 IsUnverifiable, ///< Can't be verified by a checker
147
148 IsSyscall, ///< Causes a system call to be emulated in syscall
149 /// emulation mode.
150
151 //Flags for microcode
152 IsMacroop, ///< Is a macroop containing microops
153 IsMicroop, ///< Is a microop
154 IsDelayedCommit, ///< This microop doesn't commit right away
155 IsLastMicroop, ///< This microop ends a microop sequence
156 IsFirstMicroop, ///< This microop begins a microop sequence
157 //This flag doesn't do anything yet
158 IsMicroBranch, ///< This microop branches within the microcode for a macroop
159 IsDspOp,
160 IsSquashAfter, ///< Squash all uncommitted state after executed
161 NumFlags
162 };
163
164 protected:
165
166 /// Flag values for this instruction.
167 std::bitset<NumFlags> flags;
168
169 /// See opClass().
170 OpClass _opClass;
171
172 /// See numSrcRegs().
173 int8_t _numSrcRegs;
174
175 /// See numDestRegs().
176 int8_t _numDestRegs;
177
178 /// The following are used to track physical register usage
179 /// for machines with separate int & FP reg files.
180 //@{
181 int8_t _numFPDestRegs;
182 int8_t _numIntDestRegs;
183 //@}
184
185 /// Constructor.
186 /// It's important to initialize everything here to a sane
187 /// default, since the decoder generally only overrides
188 /// the fields that are meaningful for the particular
189 /// instruction.
190 StaticInstBase(OpClass __opClass)
191 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
192 _numFPDestRegs(0), _numIntDestRegs(0)
193 {
194 }
195
196 public:
197
198 /// @name Register information.
199 /// The sum of numFPDestRegs() and numIntDestRegs() equals
200 /// numDestRegs(). The former two functions are used to track
201 /// physical register usage for machines with separate int & FP
202 /// reg files.
203 //@{
204 /// Number of source registers.
205 int8_t numSrcRegs() const { return _numSrcRegs; }
206 /// Number of destination registers.
207 int8_t numDestRegs() const { return _numDestRegs; }
208 /// Number of floating-point destination regs.
209 int8_t numFPDestRegs() const { return _numFPDestRegs; }
210 /// Number of integer destination regs.
211 int8_t numIntDestRegs() const { return _numIntDestRegs; }
212 //@}
213
214 /// @name Flag accessors.
215 /// These functions are used to access the values of the various
216 /// instruction property flags. See StaticInstBase::Flags for descriptions
217 /// of the individual flags.
218 //@{
219
220 bool isNop() const { return flags[IsNop]; }
221
222 bool isMemRef() const { return flags[IsMemRef]; }
223 bool isLoad() const { return flags[IsLoad]; }
224 bool isStore() const { return flags[IsStore]; }
225 bool isStoreConditional() const { return flags[IsStoreConditional]; }
226 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
227 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
228 bool isPrefetch() const { return isInstPrefetch() ||
229 isDataPrefetch(); }
230
231 bool isInteger() const { return flags[IsInteger]; }
232 bool isFloating() const { return flags[IsFloating]; }
233
234 bool isControl() const { return flags[IsControl]; }
235 bool isCall() const { return flags[IsCall]; }
236 bool isReturn() const { return flags[IsReturn]; }
237 bool isDirectCtrl() const { return flags[IsDirectControl]; }
238 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
239 bool isCondCtrl() const { return flags[IsCondControl]; }
240 bool isUncondCtrl() const { return flags[IsUncondControl]; }
241 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
242
243 bool isThreadSync() const { return flags[IsThreadSync]; }
244 bool isSerializing() const { return flags[IsSerializing] ||
245 flags[IsSerializeBefore] ||
246 flags[IsSerializeAfter]; }
247 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
248 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
249 bool isSquashAfter() const { return flags[IsSquashAfter]; }
250 bool isMemBarrier() const { return flags[IsMemBarrier]; }
251 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
252 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
253 bool isQuiesce() const { return flags[IsQuiesce]; }
254 bool isIprAccess() const { return flags[IsIprAccess]; }
255 bool isUnverifiable() const { return flags[IsUnverifiable]; }
256 bool isSyscall() const { return flags[IsSyscall]; }
257 bool isMacroop() const { return flags[IsMacroop]; }
258 bool isMicroop() const { return flags[IsMicroop]; }
259 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
260 bool isLastMicroop() const { return flags[IsLastMicroop]; }
261 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
262 //This flag doesn't do anything yet
263 bool isMicroBranch() const { return flags[IsMicroBranch]; }
264 //@}
265
266 void setLastMicroop() { flags[IsLastMicroop] = true; }
267 void setDelayedCommit() { flags[IsDelayedCommit] = true; }
268 void setFlag(Flags f) { flags[f] = true; }
269
270 /// Operation class. Used to select appropriate function unit in issue.
271 OpClass opClass() const { return _opClass; }
272};
273
274
275// forward declaration
276class StaticInstPtr;
277
278/**
279 * Generic yet ISA-dependent static instruction class.
280 *
281 * This class builds on StaticInstBase, defining fields and interfaces
282 * that are generic across all ISAs but that differ in details
283 * according to the specific ISA being used.
284 */
285class StaticInst : public StaticInstBase
286{
287 public:
66
67namespace Trace {
68 class InstRecord;
69}
70
71/**
72 * Base, ISA-independent static instruction class.
73 *
74 * The main component of this class is the vector of flags and the
75 * associated methods for reading them. Any object that can rely
76 * solely on these flags can process instructions without being
77 * recompiled for multiple ISAs.
78 */
79class StaticInstBase : public RefCounted
80{
81 public:
82
83 /// Set of boolean static instruction properties.
84 ///
85 /// Notes:
86 /// - The IsInteger and IsFloating flags are based on the class of
87 /// registers accessed by the instruction. Although most
88 /// instructions will have exactly one of these two flags set, it
89 /// is possible for an instruction to have neither (e.g., direct
90 /// unconditional branches, memory barriers) or both (e.g., an
91 /// FP/int conversion).
92 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
93 /// will be set.
94 /// - If IsControl is set, then exactly one of IsDirectControl or
95 /// IsIndirect Control will be set, and exactly one of
96 /// IsCondControl or IsUncondControl will be set.
97 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
98 /// implemented as flags since in the current model there's no
99 /// other way for instructions to inject behavior into the
100 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
101 /// model we should be able to get rid of these flags and
102 /// implement this behavior via the execute() methods.
103 ///
104 enum Flags {
105 IsNop, ///< Is a no-op (no effect at all).
106
107 IsInteger, ///< References integer regs.
108 IsFloating, ///< References FP regs.
109
110 IsMemRef, ///< References memory (load, store, or prefetch).
111 IsLoad, ///< Reads from memory (load or prefetch).
112 IsStore, ///< Writes to memory.
113 IsStoreConditional, ///< Store conditional instruction.
114 IsIndexed, ///< Accesses memory with an indexed address computation
115 IsInstPrefetch, ///< Instruction-cache prefetch.
116 IsDataPrefetch, ///< Data-cache prefetch.
117
118 IsControl, ///< Control transfer instruction.
119 IsDirectControl, ///< PC relative control transfer.
120 IsIndirectControl, ///< Register indirect control transfer.
121 IsCondControl, ///< Conditional control transfer.
122 IsUncondControl, ///< Unconditional control transfer.
123 IsCall, ///< Subroutine call.
124 IsReturn, ///< Subroutine return.
125
126 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
127
128 IsThreadSync, ///< Thread synchronization operation.
129
130 IsSerializing, ///< Serializes pipeline: won't execute until all
131 /// older instructions have committed.
132 IsSerializeBefore,
133 IsSerializeAfter,
134 IsMemBarrier, ///< Is a memory barrier
135 IsWriteBarrier, ///< Is a write barrier
136 IsReadBarrier, ///< Is a read barrier
137 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
138
139 IsNonSpeculative, ///< Should not be executed speculatively
140 IsQuiesce, ///< Is a quiesce instruction
141
142 IsIprAccess, ///< Accesses IPRs
143 IsUnverifiable, ///< Can't be verified by a checker
144
145 IsSyscall, ///< Causes a system call to be emulated in syscall
146 /// emulation mode.
147
148 //Flags for microcode
149 IsMacroop, ///< Is a macroop containing microops
150 IsMicroop, ///< Is a microop
151 IsDelayedCommit, ///< This microop doesn't commit right away
152 IsLastMicroop, ///< This microop ends a microop sequence
153 IsFirstMicroop, ///< This microop begins a microop sequence
154 //This flag doesn't do anything yet
155 IsMicroBranch, ///< This microop branches within the microcode for a macroop
156 IsDspOp,
157 IsSquashAfter, ///< Squash all uncommitted state after executed
158 NumFlags
159 };
160
161 protected:
162
163 /// Flag values for this instruction.
164 std::bitset<NumFlags> flags;
165
166 /// See opClass().
167 OpClass _opClass;
168
169 /// See numSrcRegs().
170 int8_t _numSrcRegs;
171
172 /// See numDestRegs().
173 int8_t _numDestRegs;
174
175 /// The following are used to track physical register usage
176 /// for machines with separate int & FP reg files.
177 //@{
178 int8_t _numFPDestRegs;
179 int8_t _numIntDestRegs;
180 //@}
181
182 /// Constructor.
183 /// It's important to initialize everything here to a sane
184 /// default, since the decoder generally only overrides
185 /// the fields that are meaningful for the particular
186 /// instruction.
187 StaticInstBase(OpClass __opClass)
188 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
189 _numFPDestRegs(0), _numIntDestRegs(0)
190 {
191 }
192
193 public:
194
195 /// @name Register information.
196 /// The sum of numFPDestRegs() and numIntDestRegs() equals
197 /// numDestRegs(). The former two functions are used to track
198 /// physical register usage for machines with separate int & FP
199 /// reg files.
200 //@{
201 /// Number of source registers.
202 int8_t numSrcRegs() const { return _numSrcRegs; }
203 /// Number of destination registers.
204 int8_t numDestRegs() const { return _numDestRegs; }
205 /// Number of floating-point destination regs.
206 int8_t numFPDestRegs() const { return _numFPDestRegs; }
207 /// Number of integer destination regs.
208 int8_t numIntDestRegs() const { return _numIntDestRegs; }
209 //@}
210
211 /// @name Flag accessors.
212 /// These functions are used to access the values of the various
213 /// instruction property flags. See StaticInstBase::Flags for descriptions
214 /// of the individual flags.
215 //@{
216
217 bool isNop() const { return flags[IsNop]; }
218
219 bool isMemRef() const { return flags[IsMemRef]; }
220 bool isLoad() const { return flags[IsLoad]; }
221 bool isStore() const { return flags[IsStore]; }
222 bool isStoreConditional() const { return flags[IsStoreConditional]; }
223 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
224 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
225 bool isPrefetch() const { return isInstPrefetch() ||
226 isDataPrefetch(); }
227
228 bool isInteger() const { return flags[IsInteger]; }
229 bool isFloating() const { return flags[IsFloating]; }
230
231 bool isControl() const { return flags[IsControl]; }
232 bool isCall() const { return flags[IsCall]; }
233 bool isReturn() const { return flags[IsReturn]; }
234 bool isDirectCtrl() const { return flags[IsDirectControl]; }
235 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
236 bool isCondCtrl() const { return flags[IsCondControl]; }
237 bool isUncondCtrl() const { return flags[IsUncondControl]; }
238 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
239
240 bool isThreadSync() const { return flags[IsThreadSync]; }
241 bool isSerializing() const { return flags[IsSerializing] ||
242 flags[IsSerializeBefore] ||
243 flags[IsSerializeAfter]; }
244 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
245 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
246 bool isSquashAfter() const { return flags[IsSquashAfter]; }
247 bool isMemBarrier() const { return flags[IsMemBarrier]; }
248 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
249 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
250 bool isQuiesce() const { return flags[IsQuiesce]; }
251 bool isIprAccess() const { return flags[IsIprAccess]; }
252 bool isUnverifiable() const { return flags[IsUnverifiable]; }
253 bool isSyscall() const { return flags[IsSyscall]; }
254 bool isMacroop() const { return flags[IsMacroop]; }
255 bool isMicroop() const { return flags[IsMicroop]; }
256 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
257 bool isLastMicroop() const { return flags[IsLastMicroop]; }
258 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
259 //This flag doesn't do anything yet
260 bool isMicroBranch() const { return flags[IsMicroBranch]; }
261 //@}
262
263 void setLastMicroop() { flags[IsLastMicroop] = true; }
264 void setDelayedCommit() { flags[IsDelayedCommit] = true; }
265 void setFlag(Flags f) { flags[f] = true; }
266
267 /// Operation class. Used to select appropriate function unit in issue.
268 OpClass opClass() const { return _opClass; }
269};
270
271
272// forward declaration
273class StaticInstPtr;
274
275/**
276 * Generic yet ISA-dependent static instruction class.
277 *
278 * This class builds on StaticInstBase, defining fields and interfaces
279 * that are generic across all ISAs but that differ in details
280 * according to the specific ISA being used.
281 */
282class StaticInst : public StaticInstBase
283{
284 public:
288
289 /// Binary machine instruction type.
290 typedef TheISA::MachInst MachInst;
291 /// Binary extended machine instruction type.
292 typedef TheISA::ExtMachInst ExtMachInst;
293 /// Logical register index type.
294 typedef TheISA::RegIndex RegIndex;
295
296 enum {
297 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
298 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
299 };
300
301
302 /// Return logical index (architectural reg num) of i'th destination reg.
303 /// Only the entries from 0 through numDestRegs()-1 are valid.
304 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
305
306 /// Return logical index (architectural reg num) of i'th source reg.
307 /// Only the entries from 0 through numSrcRegs()-1 are valid.
308 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
309
310 /// Pointer to a statically allocated "null" instruction object.
311 /// Used to give eaCompInst() and memAccInst() something to return
312 /// when called on non-memory instructions.
313 static StaticInstPtr nullStaticInstPtr;
314
315 /**
316 * Memory references only: returns "fake" instruction representing
317 * the effective address part of the memory operation. Used to
318 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
319 * just the EA computation.
320 */
321 virtual const
322 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
323
324 /**
325 * Memory references only: returns "fake" instruction representing
326 * the memory access part of the memory operation. Used to
327 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
328 * just the memory access (not the EA computation).
329 */
330 virtual const
331 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
332
333 /// The binary machine instruction.
334 const ExtMachInst machInst;
335
336 protected:
337
338 /// See destRegIdx().
339 RegIndex _destRegIdx[MaxInstDestRegs];
340 /// See srcRegIdx().
341 RegIndex _srcRegIdx[MaxInstSrcRegs];
342
343 /**
344 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
345 * methods. Also useful to readily identify instructions from
346 * within the debugger when #cachedDisassembly has not been
347 * initialized.
348 */
349 const char *mnemonic;
350
351 /**
352 * String representation of disassembly (lazily evaluated via
353 * disassemble()).
354 */
355 mutable std::string *cachedDisassembly;
356
357 /**
358 * Internal function to generate disassembly string.
359 */
360 virtual std::string
361 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
362
363 /// Constructor.
364 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
365 : StaticInstBase(__opClass),
366 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
367 { }
368
369 public:
370 virtual ~StaticInst();
371
372/**
373 * The execute() signatures are auto-generated by scons based on the
374 * set of CPU models we are compiling in today.
375 */
376#include "cpu/static_inst_exec_sigs.hh"
377
378 virtual void advancePC(TheISA::PCState &pcState) const = 0;
379
380 /**
381 * Return the microop that goes with a particular micropc. This should
382 * only be defined/used in macroops which will contain microops
383 */
384 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
385
386 /**
387 * Return the target address for a PC-relative branch.
388 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
389 * should be true).
390 */
391 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
392
393 /**
394 * Return the target address for an indirect branch (jump). The
395 * register value is read from the supplied thread context, so
396 * the result is valid only if the thread context is about to
397 * execute the branch in question. Invalid if not an indirect
398 * branch (i.e. isIndirectCtrl() should be true).
399 */
400 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
401
402 /**
403 * Return true if the instruction is a control transfer, and if so,
404 * return the target address as well.
405 */
406 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
407 TheISA::PCState &tgt) const;
408
409 /**
410 * Return string representation of disassembled instruction.
411 * The default version of this function will call the internal
412 * virtual generateDisassembly() function to get the string,
413 * then cache it in #cachedDisassembly. If the disassembly
414 * should not be cached, this function should be overridden directly.
415 */
416 virtual const std::string &disassemble(Addr pc,
417 const SymbolTable *symtab = 0) const;
418
285 /// Binary extended machine instruction type.
286 typedef TheISA::ExtMachInst ExtMachInst;
287 /// Logical register index type.
288 typedef TheISA::RegIndex RegIndex;
289
290 enum {
291 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
292 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
293 };
294
295
296 /// Return logical index (architectural reg num) of i'th destination reg.
297 /// Only the entries from 0 through numDestRegs()-1 are valid.
298 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
299
300 /// Return logical index (architectural reg num) of i'th source reg.
301 /// Only the entries from 0 through numSrcRegs()-1 are valid.
302 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
303
304 /// Pointer to a statically allocated "null" instruction object.
305 /// Used to give eaCompInst() and memAccInst() something to return
306 /// when called on non-memory instructions.
307 static StaticInstPtr nullStaticInstPtr;
308
309 /**
310 * Memory references only: returns "fake" instruction representing
311 * the effective address part of the memory operation. Used to
312 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
313 * just the EA computation.
314 */
315 virtual const
316 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
317
318 /**
319 * Memory references only: returns "fake" instruction representing
320 * the memory access part of the memory operation. Used to
321 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
322 * just the memory access (not the EA computation).
323 */
324 virtual const
325 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
326
327 /// The binary machine instruction.
328 const ExtMachInst machInst;
329
330 protected:
331
332 /// See destRegIdx().
333 RegIndex _destRegIdx[MaxInstDestRegs];
334 /// See srcRegIdx().
335 RegIndex _srcRegIdx[MaxInstSrcRegs];
336
337 /**
338 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
339 * methods. Also useful to readily identify instructions from
340 * within the debugger when #cachedDisassembly has not been
341 * initialized.
342 */
343 const char *mnemonic;
344
345 /**
346 * String representation of disassembly (lazily evaluated via
347 * disassemble()).
348 */
349 mutable std::string *cachedDisassembly;
350
351 /**
352 * Internal function to generate disassembly string.
353 */
354 virtual std::string
355 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
356
357 /// Constructor.
358 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
359 : StaticInstBase(__opClass),
360 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
361 { }
362
363 public:
364 virtual ~StaticInst();
365
366/**
367 * The execute() signatures are auto-generated by scons based on the
368 * set of CPU models we are compiling in today.
369 */
370#include "cpu/static_inst_exec_sigs.hh"
371
372 virtual void advancePC(TheISA::PCState &pcState) const = 0;
373
374 /**
375 * Return the microop that goes with a particular micropc. This should
376 * only be defined/used in macroops which will contain microops
377 */
378 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
379
380 /**
381 * Return the target address for a PC-relative branch.
382 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
383 * should be true).
384 */
385 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
386
387 /**
388 * Return the target address for an indirect branch (jump). The
389 * register value is read from the supplied thread context, so
390 * the result is valid only if the thread context is about to
391 * execute the branch in question. Invalid if not an indirect
392 * branch (i.e. isIndirectCtrl() should be true).
393 */
394 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
395
396 /**
397 * Return true if the instruction is a control transfer, and if so,
398 * return the target address as well.
399 */
400 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
401 TheISA::PCState &tgt) const;
402
403 /**
404 * Return string representation of disassembled instruction.
405 * The default version of this function will call the internal
406 * virtual generateDisassembly() function to get the string,
407 * then cache it in #cachedDisassembly. If the disassembly
408 * should not be cached, this function should be overridden directly.
409 */
410 virtual const std::string &disassemble(Addr pc,
411 const SymbolTable *symtab = 0) const;
412
419 /// Decoded instruction cache type.
420 /// For now we're using a generic hash_map; this seems to work
421 /// pretty well.
422 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
423
424 /// A cache of decoded instruction objects.
425 static DecodeCache decodeCache;
426
427 /**
428 * Dump some basic stats on the decode cache hash map.
429 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
430 */
431 static void dumpDecodeCacheStats();
432
433 /// Decode a machine instruction.
434 /// @param mach_inst The binary instruction to decode.
435 /// @retval A pointer to the corresponding StaticInst object.
436 //This is defined as inlined below.
437 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
438
439 /// Return name of machine instruction
440 std::string getName() { return mnemonic; }
413 /// Return name of machine instruction
414 std::string getName() { return mnemonic; }
441
442 /// Decoded instruction cache type, for address decoding.
443 /// A generic hash_map is used.
444 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
445
446 /// A cache of decoded instruction objects from addresses.
447 static AddrDecodeCache addrDecodeCache;
448
449 struct cacheElement
450 {
451 Addr page_addr;
452 AddrDecodePage *decodePage;
453
454 cacheElement() : decodePage(NULL) { }
455 };
456
457 /// An array of recently decoded instructions.
458 // might not use an array if there is only two elements
459 static struct cacheElement recentDecodes[2];
460
461 /// Updates the recently decoded instructions entries
462 /// @param page_addr The page address recently used.
463 /// @param decodePage Pointer to decoding page containing the decoded
464 /// instruction.
465 static inline void
466 updateCache(Addr page_addr, AddrDecodePage *decodePage)
467 {
468 recentDecodes[1].page_addr = recentDecodes[0].page_addr;
469 recentDecodes[1].decodePage = recentDecodes[0].decodePage;
470 recentDecodes[0].page_addr = page_addr;
471 recentDecodes[0].decodePage = decodePage;
472 }
473
474 /// Searches the decoded instruction cache for instruction decoding.
475 /// If it is not found, then we decode the instruction.
476 /// Otherwise, we get the instruction from the cache and move it into
477 /// the address-to-instruction decoding page.
478 /// @param mach_inst The binary instruction to decode.
479 /// @param addr The address that contained the binary instruction.
480 /// @param decodePage Pointer to decoding page containing the instruction.
481 /// @retval A pointer to the corresponding StaticInst object.
482 //This is defined as inlined below.
483 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
484 AddrDecodePage *decodePage);
485};
486
487typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
488
489/// Reference-counted pointer to a StaticInst object.
490/// This type should be used instead of "StaticInst *" so that
491/// StaticInst objects can be properly reference-counted.
492class StaticInstPtr : public RefCountingPtr<StaticInst>
493{
494 public:
495 /// Constructor.
496 StaticInstPtr()
497 : RefCountingPtr<StaticInst>()
498 {
499 }
500
501 /// Conversion from "StaticInst *".
502 StaticInstPtr(StaticInst *p)
503 : RefCountingPtr<StaticInst>(p)
504 {
505 }
506
507 /// Copy constructor.
508 StaticInstPtr(const StaticInstPtr &r)
509 : RefCountingPtr<StaticInst>(r)
510 {
511 }
512
415};
416
417typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
418
419/// Reference-counted pointer to a StaticInst object.
420/// This type should be used instead of "StaticInst *" so that
421/// StaticInst objects can be properly reference-counted.
422class StaticInstPtr : public RefCountingPtr<StaticInst>
423{
424 public:
425 /// Constructor.
426 StaticInstPtr()
427 : RefCountingPtr<StaticInst>()
428 {
429 }
430
431 /// Conversion from "StaticInst *".
432 StaticInstPtr(StaticInst *p)
433 : RefCountingPtr<StaticInst>(p)
434 {
435 }
436
437 /// Copy constructor.
438 StaticInstPtr(const StaticInstPtr &r)
439 : RefCountingPtr<StaticInst>(r)
440 {
441 }
442
513 /// Construct directly from machine instruction.
514 /// Calls StaticInst::decode().
515 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
516 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
517 {
518 }
519
520 /// Convert to pointer to StaticInstBase class.
521 operator const StaticInstBasePtr()
522 {
523 return this->get();
524 }
525};
526
443 /// Convert to pointer to StaticInstBase class.
444 operator const StaticInstBasePtr()
445 {
446 return this->get();
447 }
448};
449
527/// A page of a list of decoded instructions from an address.
528class AddrDecodePage
529{
530 typedef TheISA::ExtMachInst ExtMachInst;
531 protected:
532 StaticInstPtr instructions[TheISA::PageBytes];
533 bool valid[TheISA::PageBytes];
534 Addr lowerMask;
535
536 public:
537 /// Constructor
538 AddrDecodePage()
539 {
540 lowerMask = TheISA::PageBytes - 1;
541 memset(valid, 0, TheISA::PageBytes);
542 }
543
544 /// Checks if the instruction is already decoded and the machine
545 /// instruction in the cache matches the current machine instruction
546 /// related to the address
547 /// @param mach_inst The binary instruction to check
548 /// @param addr The address containing the instruction
549 bool
550 decoded(ExtMachInst mach_inst, Addr addr)
551 {
552 return (valid[addr & lowerMask] &&
553 (instructions[addr & lowerMask]->machInst == mach_inst));
554 }
555
556 /// Returns the instruction object. decoded should be called first
557 /// to check if the instruction is valid.
558 /// @param addr The address of the instruction.
559 /// @retval A pointer to the corresponding StaticInst object.
560 StaticInstPtr
561 getInst(Addr addr)
562 {
563 return instructions[addr & lowerMask];
564 }
565
566 /// Inserts a pointer to a StaticInst object into the list of decoded
567 /// instructions on the page.
568 /// @param addr The address of the instruction.
569 /// @param si A pointer to the corresponding StaticInst object.
570 void
571 insert(Addr addr, StaticInstPtr &si)
572 {
573 instructions[addr & lowerMask] = si;
574 valid[addr & lowerMask] = true;
575 }
576};
577
578
579inline StaticInstPtr
580StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
581{
582#ifdef DECODE_CACHE_HASH_STATS
583 // Simple stats on decode hash_map. Turns out the default
584 // hash function is as good as anything I could come up with.
585 const int dump_every_n = 10000000;
586 static int decodes_til_dump = dump_every_n;
587
588 if (--decodes_til_dump == 0) {
589 dumpDecodeCacheStats();
590 decodes_til_dump = dump_every_n;
591 }
592#endif
593
594 Addr page_addr = addr & ~(TheISA::PageBytes - 1);
595
596 // checks recently decoded addresses
597 if (recentDecodes[0].decodePage &&
598 page_addr == recentDecodes[0].page_addr) {
599 if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
600 return recentDecodes[0].decodePage->getInst(addr);
601
602 return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
603 }
604
605 if (recentDecodes[1].decodePage &&
606 page_addr == recentDecodes[1].page_addr) {
607 if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
608 return recentDecodes[1].decodePage->getInst(addr);
609
610 return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
611 }
612
613 // searches the page containing the address to decode
614 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
615 if (iter != addrDecodeCache.end()) {
616 updateCache(page_addr, iter->second);
617 if (iter->second->decoded(mach_inst, addr))
618 return iter->second->getInst(addr);
619
620 return searchCache(mach_inst, addr, iter->second);
621 }
622
623 // creates a new object for a page of decoded instructions
624 AddrDecodePage *decodePage = new AddrDecodePage;
625 addrDecodeCache[page_addr] = decodePage;
626 updateCache(page_addr, decodePage);
627 return searchCache(mach_inst, addr, decodePage);
628}
629
630inline StaticInstPtr
631StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
632 AddrDecodePage *decodePage)
633{
634 DecodeCache::iterator iter = decodeCache.find(mach_inst);
635 if (iter != decodeCache.end()) {
636 decodePage->insert(addr, iter->second);
637 return iter->second;
638 }
639
640 StaticInstPtr si = TheISA::decodeInst(mach_inst);
641 decodePage->insert(addr, si);
642 decodeCache[mach_inst] = si;
643 return si;
644}
645
646#endif // __CPU_STATIC_INST_HH__
450#endif // __CPU_STATIC_INST_HH__