1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "arch/utility.hh"
39#include "sim/faults.hh"
40#include "base/bitfield.hh"
41#include "base/hashmap.hh"
42#include "base/misc.hh"
43#include "base/refcnt.hh"
44#include "cpu/op_class.hh"
45#include "sim/faults.hh"
46#include "sim/host.hh"
47
48// forward declarations
49struct AlphaSimpleImpl;
50struct OzoneImpl;
51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56class O3CPUImpl;
57template <class Impl> class BaseO3DynInst;
58typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
59template <class Impl> class OzoneDynInst;
60class InOrderDynInst;
61
62class CheckerCPU;
63class FastCPU;
64class AtomicSimpleCPU;
65class TimingSimpleCPU;
66class InorderCPU;
67class SymbolTable;
68class AddrDecodePage;
69
70namespace Trace {
71 class InstRecord;
72}
73
74typedef uint16_t MicroPC;
75
76static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1);
77
78static inline MicroPC
79romMicroPC(MicroPC upc)
80{
81 return upc | MicroPCRomBit;
82}
83
84static inline MicroPC
85normalMicroPC(MicroPC upc)
86{
87 return upc & ~MicroPCRomBit;
88}
89
90static inline bool
91isRomMicroPC(MicroPC upc)
92{
93 return MicroPCRomBit & upc;
94}
95
96/**
97 * Base, ISA-independent static instruction class.
98 *
99 * The main component of this class is the vector of flags and the
100 * associated methods for reading them. Any object that can rely
101 * solely on these flags can process instructions without being
102 * recompiled for multiple ISAs.
103 */
104class StaticInstBase : public RefCounted
105{
106 protected:
107
108 /// Set of boolean static instruction properties.
109 ///
110 /// Notes:
111 /// - The IsInteger and IsFloating flags are based on the class of
112 /// registers accessed by the instruction. Although most
113 /// instructions will have exactly one of these two flags set, it
114 /// is possible for an instruction to have neither (e.g., direct
115 /// unconditional branches, memory barriers) or both (e.g., an
116 /// FP/int conversion).
117 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
118 /// will be set.
119 /// - If IsControl is set, then exactly one of IsDirectControl or
120 /// IsIndirect Control will be set, and exactly one of
121 /// IsCondControl or IsUncondControl will be set.
122 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
123 /// implemented as flags since in the current model there's no
124 /// other way for instructions to inject behavior into the
125 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
126 /// model we should be able to get rid of these flags and
127 /// implement this behavior via the execute() methods.
128 ///
129 enum Flags {
130 IsNop, ///< Is a no-op (no effect at all).
131
132 IsInteger, ///< References integer regs.
133 IsFloating, ///< References FP regs.
134
135 IsMemRef, ///< References memory (load, store, or prefetch).
136 IsLoad, ///< Reads from memory (load or prefetch).
137 IsStore, ///< Writes to memory.
138 IsStoreConditional, ///< Store conditional instruction.
139 IsIndexed, ///< Accesses memory with an indexed address computation
140 IsInstPrefetch, ///< Instruction-cache prefetch.
141 IsDataPrefetch, ///< Data-cache prefetch.
142 IsCopy, ///< Fast Cache block copy
143
144 IsControl, ///< Control transfer instruction.
145 IsDirectControl, ///< PC relative control transfer.
146 IsIndirectControl, ///< Register indirect control transfer.
147 IsCondControl, ///< Conditional control transfer.
148 IsUncondControl, ///< Unconditional control transfer.
149 IsCall, ///< Subroutine call.
150 IsReturn, ///< Subroutine return.
151
152 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
153
154 IsThreadSync, ///< Thread synchronization operation.
155
156 IsSerializing, ///< Serializes pipeline: won't execute until all
157 /// older instructions have committed.
158 IsSerializeBefore,
159 IsSerializeAfter,
160 IsMemBarrier, ///< Is a memory barrier
161 IsWriteBarrier, ///< Is a write barrier
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "arch/utility.hh"
39#include "sim/faults.hh"
40#include "base/bitfield.hh"
41#include "base/hashmap.hh"
42#include "base/misc.hh"
43#include "base/refcnt.hh"
44#include "cpu/op_class.hh"
45#include "sim/faults.hh"
46#include "sim/host.hh"
47
48// forward declarations
49struct AlphaSimpleImpl;
50struct OzoneImpl;
51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56class O3CPUImpl;
57template <class Impl> class BaseO3DynInst;
58typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
59template <class Impl> class OzoneDynInst;
60class InOrderDynInst;
61
62class CheckerCPU;
63class FastCPU;
64class AtomicSimpleCPU;
65class TimingSimpleCPU;
66class InorderCPU;
67class SymbolTable;
68class AddrDecodePage;
69
70namespace Trace {
71 class InstRecord;
72}
73
74typedef uint16_t MicroPC;
75
76static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1);
77
78static inline MicroPC
79romMicroPC(MicroPC upc)
80{
81 return upc | MicroPCRomBit;
82}
83
84static inline MicroPC
85normalMicroPC(MicroPC upc)
86{
87 return upc & ~MicroPCRomBit;
88}
89
90static inline bool
91isRomMicroPC(MicroPC upc)
92{
93 return MicroPCRomBit & upc;
94}
95
96/**
97 * Base, ISA-independent static instruction class.
98 *
99 * The main component of this class is the vector of flags and the
100 * associated methods for reading them. Any object that can rely
101 * solely on these flags can process instructions without being
102 * recompiled for multiple ISAs.
103 */
104class StaticInstBase : public RefCounted
105{
106 protected:
107
108 /// Set of boolean static instruction properties.
109 ///
110 /// Notes:
111 /// - The IsInteger and IsFloating flags are based on the class of
112 /// registers accessed by the instruction. Although most
113 /// instructions will have exactly one of these two flags set, it
114 /// is possible for an instruction to have neither (e.g., direct
115 /// unconditional branches, memory barriers) or both (e.g., an
116 /// FP/int conversion).
117 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
118 /// will be set.
119 /// - If IsControl is set, then exactly one of IsDirectControl or
120 /// IsIndirect Control will be set, and exactly one of
121 /// IsCondControl or IsUncondControl will be set.
122 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
123 /// implemented as flags since in the current model there's no
124 /// other way for instructions to inject behavior into the
125 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
126 /// model we should be able to get rid of these flags and
127 /// implement this behavior via the execute() methods.
128 ///
129 enum Flags {
130 IsNop, ///< Is a no-op (no effect at all).
131
132 IsInteger, ///< References integer regs.
133 IsFloating, ///< References FP regs.
134
135 IsMemRef, ///< References memory (load, store, or prefetch).
136 IsLoad, ///< Reads from memory (load or prefetch).
137 IsStore, ///< Writes to memory.
138 IsStoreConditional, ///< Store conditional instruction.
139 IsIndexed, ///< Accesses memory with an indexed address computation
140 IsInstPrefetch, ///< Instruction-cache prefetch.
141 IsDataPrefetch, ///< Data-cache prefetch.
142 IsCopy, ///< Fast Cache block copy
143
144 IsControl, ///< Control transfer instruction.
145 IsDirectControl, ///< PC relative control transfer.
146 IsIndirectControl, ///< Register indirect control transfer.
147 IsCondControl, ///< Conditional control transfer.
148 IsUncondControl, ///< Unconditional control transfer.
149 IsCall, ///< Subroutine call.
150 IsReturn, ///< Subroutine return.
151
152 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
153
154 IsThreadSync, ///< Thread synchronization operation.
155
156 IsSerializing, ///< Serializes pipeline: won't execute until all
157 /// older instructions have committed.
158 IsSerializeBefore,
159 IsSerializeAfter,
160 IsMemBarrier, ///< Is a memory barrier
161 IsWriteBarrier, ///< Is a write barrier
|
162 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
163
164 IsNonSpeculative, ///< Should not be executed speculatively
165 IsQuiesce, ///< Is a quiesce instruction
166
167 IsIprAccess, ///< Accesses IPRs
168 IsUnverifiable, ///< Can't be verified by a checker
169
170 IsSyscall, ///< Causes a system call to be emulated in syscall
171 /// emulation mode.
172
173 //Flags for microcode
174 IsMacroop, ///< Is a macroop containing microops
175 IsMicroop, ///< Is a microop
176 IsDelayedCommit, ///< This microop doesn't commit right away
177 IsLastMicroop, ///< This microop ends a microop sequence
178 IsFirstMicroop, ///< This microop begins a microop sequence
179 //This flag doesn't do anything yet
180 IsMicroBranch, ///< This microop branches within the microcode for a macroop
181 IsDspOp,
182
183 NumFlags
184 };
185
186 /// Flag values for this instruction.
187 std::bitset<NumFlags> flags;
188
189 /// See opClass().
190 OpClass _opClass;
191
192 /// See numSrcRegs().
193 int8_t _numSrcRegs;
194
195 /// See numDestRegs().
196 int8_t _numDestRegs;
197
198 /// The following are used to track physical register usage
199 /// for machines with separate int & FP reg files.
200 //@{
201 int8_t _numFPDestRegs;
202 int8_t _numIntDestRegs;
203 //@}
204
205 /// Constructor.
206 /// It's important to initialize everything here to a sane
207 /// default, since the decoder generally only overrides
208 /// the fields that are meaningful for the particular
209 /// instruction.
210 StaticInstBase(OpClass __opClass)
211 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
212 _numFPDestRegs(0), _numIntDestRegs(0)
213 {
214 }
215
216 public:
217
218 /// @name Register information.
219 /// The sum of numFPDestRegs() and numIntDestRegs() equals
220 /// numDestRegs(). The former two functions are used to track
221 /// physical register usage for machines with separate int & FP
222 /// reg files.
223 //@{
224 /// Number of source registers.
225 int8_t numSrcRegs() const { return _numSrcRegs; }
226 /// Number of destination registers.
227 int8_t numDestRegs() const { return _numDestRegs; }
228 /// Number of floating-point destination regs.
229 int8_t numFPDestRegs() const { return _numFPDestRegs; }
230 /// Number of integer destination regs.
231 int8_t numIntDestRegs() const { return _numIntDestRegs; }
232 //@}
233
234 /// @name Flag accessors.
235 /// These functions are used to access the values of the various
236 /// instruction property flags. See StaticInstBase::Flags for descriptions
237 /// of the individual flags.
238 //@{
239
240 bool isNop() const { return flags[IsNop]; }
241
242 bool isMemRef() const { return flags[IsMemRef]; }
243 bool isLoad() const { return flags[IsLoad]; }
244 bool isStore() const { return flags[IsStore]; }
245 bool isStoreConditional() const { return flags[IsStoreConditional]; }
246 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
247 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
248 bool isCopy() const { return flags[IsCopy];}
249
250 bool isInteger() const { return flags[IsInteger]; }
251 bool isFloating() const { return flags[IsFloating]; }
252
253 bool isControl() const { return flags[IsControl]; }
254 bool isCall() const { return flags[IsCall]; }
255 bool isReturn() const { return flags[IsReturn]; }
256 bool isDirectCtrl() const { return flags[IsDirectControl]; }
257 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
258 bool isCondCtrl() const { return flags[IsCondControl]; }
259 bool isUncondCtrl() const { return flags[IsUncondControl]; }
260 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
261
262 bool isThreadSync() const { return flags[IsThreadSync]; }
263 bool isSerializing() const { return flags[IsSerializing] ||
264 flags[IsSerializeBefore] ||
265 flags[IsSerializeAfter]; }
266 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
267 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
268 bool isMemBarrier() const { return flags[IsMemBarrier]; }
269 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
270 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
271 bool isQuiesce() const { return flags[IsQuiesce]; }
272 bool isIprAccess() const { return flags[IsIprAccess]; }
273 bool isUnverifiable() const { return flags[IsUnverifiable]; }
274 bool isSyscall() const { return flags[IsSyscall]; }
275 bool isMacroop() const { return flags[IsMacroop]; }
276 bool isMicroop() const { return flags[IsMicroop]; }
277 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
278 bool isLastMicroop() const { return flags[IsLastMicroop]; }
279 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
280 //This flag doesn't do anything yet
281 bool isMicroBranch() const { return flags[IsMicroBranch]; }
282 //@}
283
284 void setLastMicroop() { flags[IsLastMicroop] = true; }
285 /// Operation class. Used to select appropriate function unit in issue.
286 OpClass opClass() const { return _opClass; }
287};
288
289
290// forward declaration
291class StaticInstPtr;
292
293/**
294 * Generic yet ISA-dependent static instruction class.
295 *
296 * This class builds on StaticInstBase, defining fields and interfaces
297 * that are generic across all ISAs but that differ in details
298 * according to the specific ISA being used.
299 */
300class StaticInst : public StaticInstBase
301{
302 public:
303
304 /// Binary machine instruction type.
305 typedef TheISA::MachInst MachInst;
306 /// Binary extended machine instruction type.
307 typedef TheISA::ExtMachInst ExtMachInst;
308 /// Logical register index type.
309 typedef TheISA::RegIndex RegIndex;
310
311 enum {
312 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
313 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
314 };
315
316
317 /// Return logical index (architectural reg num) of i'th destination reg.
318 /// Only the entries from 0 through numDestRegs()-1 are valid.
319 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
320
321 /// Return logical index (architectural reg num) of i'th source reg.
322 /// Only the entries from 0 through numSrcRegs()-1 are valid.
323 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
324
325 /// Pointer to a statically allocated "null" instruction object.
326 /// Used to give eaCompInst() and memAccInst() something to return
327 /// when called on non-memory instructions.
328 static StaticInstPtr nullStaticInstPtr;
329
330 /**
331 * Memory references only: returns "fake" instruction representing
332 * the effective address part of the memory operation. Used to
333 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
334 * just the EA computation.
335 */
336 virtual const
337 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
338
339 /**
340 * Memory references only: returns "fake" instruction representing
341 * the memory access part of the memory operation. Used to
342 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
343 * just the memory access (not the EA computation).
344 */
345 virtual const
346 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
347
348 /// The binary machine instruction.
349 const ExtMachInst machInst;
350
351 protected:
352
353 /// See destRegIdx().
354 RegIndex _destRegIdx[MaxInstDestRegs];
355 /// See srcRegIdx().
356 RegIndex _srcRegIdx[MaxInstSrcRegs];
357
358 /**
359 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
360 * methods. Also useful to readily identify instructions from
361 * within the debugger when #cachedDisassembly has not been
362 * initialized.
363 */
364 const char *mnemonic;
365
366 /**
367 * String representation of disassembly (lazily evaluated via
368 * disassemble()).
369 */
370 mutable std::string *cachedDisassembly;
371
372 /**
373 * Internal function to generate disassembly string.
374 */
375 virtual std::string
376 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
377
378 /// Constructor.
379 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
380 : StaticInstBase(__opClass),
381 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
382 { }
383
384 public:
385 virtual ~StaticInst();
386
387/**
388 * The execute() signatures are auto-generated by scons based on the
389 * set of CPU models we are compiling in today.
390 */
391#include "cpu/static_inst_exec_sigs.hh"
392
393 /**
394 * Return the microop that goes with a particular micropc. This should
395 * only be defined/used in macroops which will contain microops
396 */
397 virtual StaticInstPtr fetchMicroop(MicroPC micropc);
398
399 /**
400 * Return the target address for a PC-relative branch.
401 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
402 * should be true).
403 */
404 virtual Addr branchTarget(Addr branchPC) const;
405
406 /**
407 * Return the target address for an indirect branch (jump). The
408 * register value is read from the supplied thread context, so
409 * the result is valid only if the thread context is about to
410 * execute the branch in question. Invalid if not an indirect
411 * branch (i.e. isIndirectCtrl() should be true).
412 */
413 virtual Addr branchTarget(ThreadContext *tc) const;
414
415 /**
416 * Return true if the instruction is a control transfer, and if so,
417 * return the target address as well.
418 */
419 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
420
421 virtual Request::Flags memAccFlags();
422
423 /**
424 * Return string representation of disassembled instruction.
425 * The default version of this function will call the internal
426 * virtual generateDisassembly() function to get the string,
427 * then cache it in #cachedDisassembly. If the disassembly
428 * should not be cached, this function should be overridden directly.
429 */
430 virtual const std::string &disassemble(Addr pc,
431 const SymbolTable *symtab = 0) const;
432
433 /// Decoded instruction cache type.
434 /// For now we're using a generic hash_map; this seems to work
435 /// pretty well.
436 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
437
438 /// A cache of decoded instruction objects.
439 static DecodeCache decodeCache;
440
441 /**
442 * Dump some basic stats on the decode cache hash map.
443 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
444 */
445 static void dumpDecodeCacheStats();
446
447 /// Decode a machine instruction.
448 /// @param mach_inst The binary instruction to decode.
449 /// @retval A pointer to the corresponding StaticInst object.
450 //This is defined as inlined below.
451 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
452
453 /// Return name of machine instruction
454 std::string getName() { return mnemonic; }
455
456 /// Decoded instruction cache type, for address decoding.
457 /// A generic hash_map is used.
458 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
459
460 /// A cache of decoded instruction objects from addresses.
461 static AddrDecodeCache addrDecodeCache;
462
463 struct cacheElement
464 {
465 Addr page_addr;
466 AddrDecodePage *decodePage;
467
468 cacheElement() : decodePage(NULL) { }
469 };
470
471 /// An array of recently decoded instructions.
472 // might not use an array if there is only two elements
473 static struct cacheElement recentDecodes[2];
474
475 /// Updates the recently decoded instructions entries
476 /// @param page_addr The page address recently used.
477 /// @param decodePage Pointer to decoding page containing the decoded
478 /// instruction.
479 static inline void
480 updateCache(Addr page_addr, AddrDecodePage *decodePage)
481 {
482 recentDecodes[1].page_addr = recentDecodes[0].page_addr;
483 recentDecodes[1].decodePage = recentDecodes[0].decodePage;
484 recentDecodes[0].page_addr = page_addr;
485 recentDecodes[0].decodePage = decodePage;
486 }
487
488 /// Searches the decoded instruction cache for instruction decoding.
489 /// If it is not found, then we decode the instruction.
490 /// Otherwise, we get the instruction from the cache and move it into
491 /// the address-to-instruction decoding page.
492 /// @param mach_inst The binary instruction to decode.
493 /// @param addr The address that contained the binary instruction.
494 /// @param decodePage Pointer to decoding page containing the instruction.
495 /// @retval A pointer to the corresponding StaticInst object.
496 //This is defined as inlined below.
497 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
498 AddrDecodePage *decodePage);
499};
500
501typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
502
503/// Reference-counted pointer to a StaticInst object.
504/// This type should be used instead of "StaticInst *" so that
505/// StaticInst objects can be properly reference-counted.
506class StaticInstPtr : public RefCountingPtr<StaticInst>
507{
508 public:
509 /// Constructor.
510 StaticInstPtr()
511 : RefCountingPtr<StaticInst>()
512 {
513 }
514
515 /// Conversion from "StaticInst *".
516 StaticInstPtr(StaticInst *p)
517 : RefCountingPtr<StaticInst>(p)
518 {
519 }
520
521 /// Copy constructor.
522 StaticInstPtr(const StaticInstPtr &r)
523 : RefCountingPtr<StaticInst>(r)
524 {
525 }
526
527 /// Construct directly from machine instruction.
528 /// Calls StaticInst::decode().
529 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
530 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
531 {
532 }
533
534 /// Convert to pointer to StaticInstBase class.
535 operator const StaticInstBasePtr()
536 {
537 return this->get();
538 }
539};
540
541/// A page of a list of decoded instructions from an address.
542class AddrDecodePage
543{
544 typedef TheISA::ExtMachInst ExtMachInst;
545 protected:
546 StaticInstPtr instructions[TheISA::PageBytes];
547 bool valid[TheISA::PageBytes];
548 Addr lowerMask;
549
550 public:
551 /// Constructor
552 AddrDecodePage()
553 {
554 lowerMask = TheISA::PageBytes - 1;
555 memset(valid, 0, TheISA::PageBytes);
556 }
557
558 /// Checks if the instruction is already decoded and the machine
559 /// instruction in the cache matches the current machine instruction
560 /// related to the address
561 /// @param mach_inst The binary instruction to check
562 /// @param addr The address containing the instruction
563 bool
564 decoded(ExtMachInst mach_inst, Addr addr)
565 {
566 return (valid[addr & lowerMask] &&
567 (instructions[addr & lowerMask]->machInst == mach_inst));
568 }
569
570 /// Returns the instruction object. decoded should be called first
571 /// to check if the instruction is valid.
572 /// @param addr The address of the instruction.
573 /// @retval A pointer to the corresponding StaticInst object.
574 StaticInstPtr
575 getInst(Addr addr)
576 {
577 return instructions[addr & lowerMask];
578 }
579
580 /// Inserts a pointer to a StaticInst object into the list of decoded
581 /// instructions on the page.
582 /// @param addr The address of the instruction.
583 /// @param si A pointer to the corresponding StaticInst object.
584 void
585 insert(Addr addr, StaticInstPtr &si)
586 {
587 instructions[addr & lowerMask] = si;
588 valid[addr & lowerMask] = true;
589 }
590};
591
592
593inline StaticInstPtr
594StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
595{
596#ifdef DECODE_CACHE_HASH_STATS
597 // Simple stats on decode hash_map. Turns out the default
598 // hash function is as good as anything I could come up with.
599 const int dump_every_n = 10000000;
600 static int decodes_til_dump = dump_every_n;
601
602 if (--decodes_til_dump == 0) {
603 dumpDecodeCacheStats();
604 decodes_til_dump = dump_every_n;
605 }
606#endif
607
608 Addr page_addr = addr & ~(TheISA::PageBytes - 1);
609
610 // checks recently decoded addresses
611 if (recentDecodes[0].decodePage &&
612 page_addr == recentDecodes[0].page_addr) {
613 if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
614 return recentDecodes[0].decodePage->getInst(addr);
615
616 return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
617 }
618
619 if (recentDecodes[1].decodePage &&
620 page_addr == recentDecodes[1].page_addr) {
621 if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
622 return recentDecodes[1].decodePage->getInst(addr);
623
624 return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
625 }
626
627 // searches the page containing the address to decode
628 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
629 if (iter != addrDecodeCache.end()) {
630 updateCache(page_addr, iter->second);
631 if (iter->second->decoded(mach_inst, addr))
632 return iter->second->getInst(addr);
633
634 return searchCache(mach_inst, addr, iter->second);
635 }
636
637 // creates a new object for a page of decoded instructions
638 AddrDecodePage *decodePage = new AddrDecodePage;
639 addrDecodeCache[page_addr] = decodePage;
640 updateCache(page_addr, decodePage);
641 return searchCache(mach_inst, addr, decodePage);
642}
643
644inline StaticInstPtr
645StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
646 AddrDecodePage *decodePage)
647{
648 DecodeCache::iterator iter = decodeCache.find(mach_inst);
649 if (iter != decodeCache.end()) {
650 decodePage->insert(addr, iter->second);
651 return iter->second;
652 }
653
654 StaticInstPtr si = TheISA::decodeInst(mach_inst);
655 decodePage->insert(addr, si);
656 decodeCache[mach_inst] = si;
657 return si;
658}
659
660#endif // __CPU_STATIC_INST_HH__
| 163 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
164
165 IsNonSpeculative, ///< Should not be executed speculatively
166 IsQuiesce, ///< Is a quiesce instruction
167
168 IsIprAccess, ///< Accesses IPRs
169 IsUnverifiable, ///< Can't be verified by a checker
170
171 IsSyscall, ///< Causes a system call to be emulated in syscall
172 /// emulation mode.
173
174 //Flags for microcode
175 IsMacroop, ///< Is a macroop containing microops
176 IsMicroop, ///< Is a microop
177 IsDelayedCommit, ///< This microop doesn't commit right away
178 IsLastMicroop, ///< This microop ends a microop sequence
179 IsFirstMicroop, ///< This microop begins a microop sequence
180 //This flag doesn't do anything yet
181 IsMicroBranch, ///< This microop branches within the microcode for a macroop
182 IsDspOp,
183
184 NumFlags
185 };
186
187 /// Flag values for this instruction.
188 std::bitset<NumFlags> flags;
189
190 /// See opClass().
191 OpClass _opClass;
192
193 /// See numSrcRegs().
194 int8_t _numSrcRegs;
195
196 /// See numDestRegs().
197 int8_t _numDestRegs;
198
199 /// The following are used to track physical register usage
200 /// for machines with separate int & FP reg files.
201 //@{
202 int8_t _numFPDestRegs;
203 int8_t _numIntDestRegs;
204 //@}
205
206 /// Constructor.
207 /// It's important to initialize everything here to a sane
208 /// default, since the decoder generally only overrides
209 /// the fields that are meaningful for the particular
210 /// instruction.
211 StaticInstBase(OpClass __opClass)
212 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
213 _numFPDestRegs(0), _numIntDestRegs(0)
214 {
215 }
216
217 public:
218
219 /// @name Register information.
220 /// The sum of numFPDestRegs() and numIntDestRegs() equals
221 /// numDestRegs(). The former two functions are used to track
222 /// physical register usage for machines with separate int & FP
223 /// reg files.
224 //@{
225 /// Number of source registers.
226 int8_t numSrcRegs() const { return _numSrcRegs; }
227 /// Number of destination registers.
228 int8_t numDestRegs() const { return _numDestRegs; }
229 /// Number of floating-point destination regs.
230 int8_t numFPDestRegs() const { return _numFPDestRegs; }
231 /// Number of integer destination regs.
232 int8_t numIntDestRegs() const { return _numIntDestRegs; }
233 //@}
234
235 /// @name Flag accessors.
236 /// These functions are used to access the values of the various
237 /// instruction property flags. See StaticInstBase::Flags for descriptions
238 /// of the individual flags.
239 //@{
240
241 bool isNop() const { return flags[IsNop]; }
242
243 bool isMemRef() const { return flags[IsMemRef]; }
244 bool isLoad() const { return flags[IsLoad]; }
245 bool isStore() const { return flags[IsStore]; }
246 bool isStoreConditional() const { return flags[IsStoreConditional]; }
247 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
248 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
249 bool isCopy() const { return flags[IsCopy];}
250
251 bool isInteger() const { return flags[IsInteger]; }
252 bool isFloating() const { return flags[IsFloating]; }
253
254 bool isControl() const { return flags[IsControl]; }
255 bool isCall() const { return flags[IsCall]; }
256 bool isReturn() const { return flags[IsReturn]; }
257 bool isDirectCtrl() const { return flags[IsDirectControl]; }
258 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
259 bool isCondCtrl() const { return flags[IsCondControl]; }
260 bool isUncondCtrl() const { return flags[IsUncondControl]; }
261 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
262
263 bool isThreadSync() const { return flags[IsThreadSync]; }
264 bool isSerializing() const { return flags[IsSerializing] ||
265 flags[IsSerializeBefore] ||
266 flags[IsSerializeAfter]; }
267 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
268 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
269 bool isMemBarrier() const { return flags[IsMemBarrier]; }
270 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
271 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
272 bool isQuiesce() const { return flags[IsQuiesce]; }
273 bool isIprAccess() const { return flags[IsIprAccess]; }
274 bool isUnverifiable() const { return flags[IsUnverifiable]; }
275 bool isSyscall() const { return flags[IsSyscall]; }
276 bool isMacroop() const { return flags[IsMacroop]; }
277 bool isMicroop() const { return flags[IsMicroop]; }
278 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
279 bool isLastMicroop() const { return flags[IsLastMicroop]; }
280 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
281 //This flag doesn't do anything yet
282 bool isMicroBranch() const { return flags[IsMicroBranch]; }
283 //@}
284
285 void setLastMicroop() { flags[IsLastMicroop] = true; }
286 /// Operation class. Used to select appropriate function unit in issue.
287 OpClass opClass() const { return _opClass; }
288};
289
290
291// forward declaration
292class StaticInstPtr;
293
294/**
295 * Generic yet ISA-dependent static instruction class.
296 *
297 * This class builds on StaticInstBase, defining fields and interfaces
298 * that are generic across all ISAs but that differ in details
299 * according to the specific ISA being used.
300 */
301class StaticInst : public StaticInstBase
302{
303 public:
304
305 /// Binary machine instruction type.
306 typedef TheISA::MachInst MachInst;
307 /// Binary extended machine instruction type.
308 typedef TheISA::ExtMachInst ExtMachInst;
309 /// Logical register index type.
310 typedef TheISA::RegIndex RegIndex;
311
312 enum {
313 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
314 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
315 };
316
317
318 /// Return logical index (architectural reg num) of i'th destination reg.
319 /// Only the entries from 0 through numDestRegs()-1 are valid.
320 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
321
322 /// Return logical index (architectural reg num) of i'th source reg.
323 /// Only the entries from 0 through numSrcRegs()-1 are valid.
324 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
325
326 /// Pointer to a statically allocated "null" instruction object.
327 /// Used to give eaCompInst() and memAccInst() something to return
328 /// when called on non-memory instructions.
329 static StaticInstPtr nullStaticInstPtr;
330
331 /**
332 * Memory references only: returns "fake" instruction representing
333 * the effective address part of the memory operation. Used to
334 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
335 * just the EA computation.
336 */
337 virtual const
338 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
339
340 /**
341 * Memory references only: returns "fake" instruction representing
342 * the memory access part of the memory operation. Used to
343 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
344 * just the memory access (not the EA computation).
345 */
346 virtual const
347 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
348
349 /// The binary machine instruction.
350 const ExtMachInst machInst;
351
352 protected:
353
354 /// See destRegIdx().
355 RegIndex _destRegIdx[MaxInstDestRegs];
356 /// See srcRegIdx().
357 RegIndex _srcRegIdx[MaxInstSrcRegs];
358
359 /**
360 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
361 * methods. Also useful to readily identify instructions from
362 * within the debugger when #cachedDisassembly has not been
363 * initialized.
364 */
365 const char *mnemonic;
366
367 /**
368 * String representation of disassembly (lazily evaluated via
369 * disassemble()).
370 */
371 mutable std::string *cachedDisassembly;
372
373 /**
374 * Internal function to generate disassembly string.
375 */
376 virtual std::string
377 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
378
379 /// Constructor.
380 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
381 : StaticInstBase(__opClass),
382 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
383 { }
384
385 public:
386 virtual ~StaticInst();
387
388/**
389 * The execute() signatures are auto-generated by scons based on the
390 * set of CPU models we are compiling in today.
391 */
392#include "cpu/static_inst_exec_sigs.hh"
393
394 /**
395 * Return the microop that goes with a particular micropc. This should
396 * only be defined/used in macroops which will contain microops
397 */
398 virtual StaticInstPtr fetchMicroop(MicroPC micropc);
399
400 /**
401 * Return the target address for a PC-relative branch.
402 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
403 * should be true).
404 */
405 virtual Addr branchTarget(Addr branchPC) const;
406
407 /**
408 * Return the target address for an indirect branch (jump). The
409 * register value is read from the supplied thread context, so
410 * the result is valid only if the thread context is about to
411 * execute the branch in question. Invalid if not an indirect
412 * branch (i.e. isIndirectCtrl() should be true).
413 */
414 virtual Addr branchTarget(ThreadContext *tc) const;
415
416 /**
417 * Return true if the instruction is a control transfer, and if so,
418 * return the target address as well.
419 */
420 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
421
422 virtual Request::Flags memAccFlags();
423
424 /**
425 * Return string representation of disassembled instruction.
426 * The default version of this function will call the internal
427 * virtual generateDisassembly() function to get the string,
428 * then cache it in #cachedDisassembly. If the disassembly
429 * should not be cached, this function should be overridden directly.
430 */
431 virtual const std::string &disassemble(Addr pc,
432 const SymbolTable *symtab = 0) const;
433
434 /// Decoded instruction cache type.
435 /// For now we're using a generic hash_map; this seems to work
436 /// pretty well.
437 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
438
439 /// A cache of decoded instruction objects.
440 static DecodeCache decodeCache;
441
442 /**
443 * Dump some basic stats on the decode cache hash map.
444 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
445 */
446 static void dumpDecodeCacheStats();
447
448 /// Decode a machine instruction.
449 /// @param mach_inst The binary instruction to decode.
450 /// @retval A pointer to the corresponding StaticInst object.
451 //This is defined as inlined below.
452 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
453
454 /// Return name of machine instruction
455 std::string getName() { return mnemonic; }
456
457 /// Decoded instruction cache type, for address decoding.
458 /// A generic hash_map is used.
459 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
460
461 /// A cache of decoded instruction objects from addresses.
462 static AddrDecodeCache addrDecodeCache;
463
464 struct cacheElement
465 {
466 Addr page_addr;
467 AddrDecodePage *decodePage;
468
469 cacheElement() : decodePage(NULL) { }
470 };
471
472 /// An array of recently decoded instructions.
473 // might not use an array if there is only two elements
474 static struct cacheElement recentDecodes[2];
475
476 /// Updates the recently decoded instructions entries
477 /// @param page_addr The page address recently used.
478 /// @param decodePage Pointer to decoding page containing the decoded
479 /// instruction.
480 static inline void
481 updateCache(Addr page_addr, AddrDecodePage *decodePage)
482 {
483 recentDecodes[1].page_addr = recentDecodes[0].page_addr;
484 recentDecodes[1].decodePage = recentDecodes[0].decodePage;
485 recentDecodes[0].page_addr = page_addr;
486 recentDecodes[0].decodePage = decodePage;
487 }
488
489 /// Searches the decoded instruction cache for instruction decoding.
490 /// If it is not found, then we decode the instruction.
491 /// Otherwise, we get the instruction from the cache and move it into
492 /// the address-to-instruction decoding page.
493 /// @param mach_inst The binary instruction to decode.
494 /// @param addr The address that contained the binary instruction.
495 /// @param decodePage Pointer to decoding page containing the instruction.
496 /// @retval A pointer to the corresponding StaticInst object.
497 //This is defined as inlined below.
498 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
499 AddrDecodePage *decodePage);
500};
501
502typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
503
504/// Reference-counted pointer to a StaticInst object.
505/// This type should be used instead of "StaticInst *" so that
506/// StaticInst objects can be properly reference-counted.
507class StaticInstPtr : public RefCountingPtr<StaticInst>
508{
509 public:
510 /// Constructor.
511 StaticInstPtr()
512 : RefCountingPtr<StaticInst>()
513 {
514 }
515
516 /// Conversion from "StaticInst *".
517 StaticInstPtr(StaticInst *p)
518 : RefCountingPtr<StaticInst>(p)
519 {
520 }
521
522 /// Copy constructor.
523 StaticInstPtr(const StaticInstPtr &r)
524 : RefCountingPtr<StaticInst>(r)
525 {
526 }
527
528 /// Construct directly from machine instruction.
529 /// Calls StaticInst::decode().
530 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
531 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
532 {
533 }
534
535 /// Convert to pointer to StaticInstBase class.
536 operator const StaticInstBasePtr()
537 {
538 return this->get();
539 }
540};
541
542/// A page of a list of decoded instructions from an address.
543class AddrDecodePage
544{
545 typedef TheISA::ExtMachInst ExtMachInst;
546 protected:
547 StaticInstPtr instructions[TheISA::PageBytes];
548 bool valid[TheISA::PageBytes];
549 Addr lowerMask;
550
551 public:
552 /// Constructor
553 AddrDecodePage()
554 {
555 lowerMask = TheISA::PageBytes - 1;
556 memset(valid, 0, TheISA::PageBytes);
557 }
558
559 /// Checks if the instruction is already decoded and the machine
560 /// instruction in the cache matches the current machine instruction
561 /// related to the address
562 /// @param mach_inst The binary instruction to check
563 /// @param addr The address containing the instruction
564 bool
565 decoded(ExtMachInst mach_inst, Addr addr)
566 {
567 return (valid[addr & lowerMask] &&
568 (instructions[addr & lowerMask]->machInst == mach_inst));
569 }
570
571 /// Returns the instruction object. decoded should be called first
572 /// to check if the instruction is valid.
573 /// @param addr The address of the instruction.
574 /// @retval A pointer to the corresponding StaticInst object.
575 StaticInstPtr
576 getInst(Addr addr)
577 {
578 return instructions[addr & lowerMask];
579 }
580
581 /// Inserts a pointer to a StaticInst object into the list of decoded
582 /// instructions on the page.
583 /// @param addr The address of the instruction.
584 /// @param si A pointer to the corresponding StaticInst object.
585 void
586 insert(Addr addr, StaticInstPtr &si)
587 {
588 instructions[addr & lowerMask] = si;
589 valid[addr & lowerMask] = true;
590 }
591};
592
593
594inline StaticInstPtr
595StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
596{
597#ifdef DECODE_CACHE_HASH_STATS
598 // Simple stats on decode hash_map. Turns out the default
599 // hash function is as good as anything I could come up with.
600 const int dump_every_n = 10000000;
601 static int decodes_til_dump = dump_every_n;
602
603 if (--decodes_til_dump == 0) {
604 dumpDecodeCacheStats();
605 decodes_til_dump = dump_every_n;
606 }
607#endif
608
609 Addr page_addr = addr & ~(TheISA::PageBytes - 1);
610
611 // checks recently decoded addresses
612 if (recentDecodes[0].decodePage &&
613 page_addr == recentDecodes[0].page_addr) {
614 if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
615 return recentDecodes[0].decodePage->getInst(addr);
616
617 return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
618 }
619
620 if (recentDecodes[1].decodePage &&
621 page_addr == recentDecodes[1].page_addr) {
622 if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
623 return recentDecodes[1].decodePage->getInst(addr);
624
625 return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
626 }
627
628 // searches the page containing the address to decode
629 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
630 if (iter != addrDecodeCache.end()) {
631 updateCache(page_addr, iter->second);
632 if (iter->second->decoded(mach_inst, addr))
633 return iter->second->getInst(addr);
634
635 return searchCache(mach_inst, addr, iter->second);
636 }
637
638 // creates a new object for a page of decoded instructions
639 AddrDecodePage *decodePage = new AddrDecodePage;
640 addrDecodeCache[page_addr] = decodePage;
641 updateCache(page_addr, decodePage);
642 return searchCache(mach_inst, addr, decodePage);
643}
644
645inline StaticInstPtr
646StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
647 AddrDecodePage *decodePage)
648{
649 DecodeCache::iterator iter = decodeCache.find(mach_inst);
650 if (iter != decodeCache.end()) {
651 decodePage->insert(addr, iter->second);
652 return iter->second;
653 }
654
655 StaticInstPtr si = TheISA::decodeInst(mach_inst);
656 decodePage->insert(addr, si);
657 decodeCache[mach_inst] = si;
658 return si;
659}
660
661#endif // __CPU_STATIC_INST_HH__
|