1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "sim/faults.hh"
39#include "base/bitfield.hh"
40#include "base/hashmap.hh"
41#include "base/misc.hh"
42#include "base/refcnt.hh"
43#include "cpu/op_class.hh"
44#include "cpu/o3/dyn_inst.hh"
45#include "sim/faults.hh"
46#include "sim/host.hh"
47
48// forward declarations
49struct AlphaSimpleImpl;
50struct OzoneImpl;
51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56template <class Impl>
57class OzoneDynInst;
58
59class CheckerCPU;
60class FastCPU;
61class AtomicSimpleCPU;
62class TimingSimpleCPU;
63class InorderCPU;
64class SymbolTable;
65
66namespace Trace {
67 class InstRecord;
68}
69
70typedef uint32_t MicroPC;
71
72/**
73 * Base, ISA-independent static instruction class.
74 *
75 * The main component of this class is the vector of flags and the
76 * associated methods for reading them. Any object that can rely
77 * solely on these flags can process instructions without being
78 * recompiled for multiple ISAs.
79 */
80class StaticInstBase : public RefCounted
81{
82 protected:
83
84 /// Set of boolean static instruction properties.
85 ///
86 /// Notes:
87 /// - The IsInteger and IsFloating flags are based on the class of
88 /// registers accessed by the instruction. Although most
89 /// instructions will have exactly one of these two flags set, it
90 /// is possible for an instruction to have neither (e.g., direct
91 /// unconditional branches, memory barriers) or both (e.g., an
92 /// FP/int conversion).
93 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
94 /// will be set.
95 /// - If IsControl is set, then exactly one of IsDirectControl or
96 /// IsIndirect Control will be set, and exactly one of
97 /// IsCondControl or IsUncondControl will be set.
98 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
99 /// implemented as flags since in the current model there's no
100 /// other way for instructions to inject behavior into the
101 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
102 /// model we should be able to get rid of these flags and
103 /// implement this behavior via the execute() methods.
104 ///
105 enum Flags {
106 IsNop, ///< Is a no-op (no effect at all).
107
108 IsInteger, ///< References integer regs.
109 IsFloating, ///< References FP regs.
110
111 IsMemRef, ///< References memory (load, store, or prefetch).
112 IsLoad, ///< Reads from memory (load or prefetch).
113 IsStore, ///< Writes to memory.
114 IsStoreConditional, ///< Store conditional instruction.
115 IsInstPrefetch, ///< Instruction-cache prefetch.
116 IsDataPrefetch, ///< Data-cache prefetch.
117 IsCopy, ///< Fast Cache block copy
118
119 IsControl, ///< Control transfer instruction.
120 IsDirectControl, ///< PC relative control transfer.
121 IsIndirectControl, ///< Register indirect control transfer.
122 IsCondControl, ///< Conditional control transfer.
123 IsUncondControl, ///< Unconditional control transfer.
124 IsCall, ///< Subroutine call.
125 IsReturn, ///< Subroutine return.
126
127 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
128
129 IsThreadSync, ///< Thread synchronization operation.
130
131 IsSerializing, ///< Serializes pipeline: won't execute until all
132 /// older instructions have committed.
133 IsSerializeBefore,
134 IsSerializeAfter,
135 IsMemBarrier, ///< Is a memory barrier
136 IsWriteBarrier, ///< Is a write barrier
137
138 IsNonSpeculative, ///< Should not be executed speculatively
139 IsQuiesce, ///< Is a quiesce instruction
140
141 IsIprAccess, ///< Accesses IPRs
142 IsUnverifiable, ///< Can't be verified by a checker
143
144 //Flags for microcode
145 IsMacroOp, ///< Is a macroop containing microops
146 IsMicroOp, ///< Is a microop
147 IsDelayedCommit, ///< This microop doesn't commit right away
148 IsLastMicroOp, ///< This microop ends a microop sequence
149 IsFirstMicroOp, ///< This microop begins a microop sequence
150 //This flag doesn't do anything yet
151 IsMicroBranch, ///< This microop branches within the microcode for a macroop
152
153 NumFlags
154 };
155
156 /// Flag values for this instruction.
157 std::bitset<NumFlags> flags;
158
159 /// See opClass().
160 OpClass _opClass;
161
162 /// See numSrcRegs().
163 int8_t _numSrcRegs;
164
165 /// See numDestRegs().
166 int8_t _numDestRegs;
167
168 /// The following are used to track physical register usage
169 /// for machines with separate int & FP reg files.
170 //@{
171 int8_t _numFPDestRegs;
172 int8_t _numIntDestRegs;
173 //@}
174
175 /// Constructor.
176 /// It's important to initialize everything here to a sane
177 /// default, since the decoder generally only overrides
178 /// the fields that are meaningful for the particular
179 /// instruction.
180 StaticInstBase(OpClass __opClass)
181 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
182 _numFPDestRegs(0), _numIntDestRegs(0)
183 {
184 }
185
186 public:
187
188 /// @name Register information.
189 /// The sum of numFPDestRegs() and numIntDestRegs() equals
190 /// numDestRegs(). The former two functions are used to track
191 /// physical register usage for machines with separate int & FP
192 /// reg files.
193 //@{
194 /// Number of source registers.
195 int8_t numSrcRegs() const { return _numSrcRegs; }
196 /// Number of destination registers.
197 int8_t numDestRegs() const { return _numDestRegs; }
198 /// Number of floating-point destination regs.
199 int8_t numFPDestRegs() const { return _numFPDestRegs; }
200 /// Number of integer destination regs.
201 int8_t numIntDestRegs() const { return _numIntDestRegs; }
202 //@}
203
204 /// @name Flag accessors.
205 /// These functions are used to access the values of the various
206 /// instruction property flags. See StaticInstBase::Flags for descriptions
207 /// of the individual flags.
208 //@{
209
210 bool isNop() const { return flags[IsNop]; }
211
212 bool isMemRef() const { return flags[IsMemRef]; }
213 bool isLoad() const { return flags[IsLoad]; }
214 bool isStore() const { return flags[IsStore]; }
215 bool isStoreConditional() const { return flags[IsStoreConditional]; }
216 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
217 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
218 bool isCopy() const { return flags[IsCopy];}
219
220 bool isInteger() const { return flags[IsInteger]; }
221 bool isFloating() const { return flags[IsFloating]; }
222
223 bool isControl() const { return flags[IsControl]; }
224 bool isCall() const { return flags[IsCall]; }
225 bool isReturn() const { return flags[IsReturn]; }
226 bool isDirectCtrl() const { return flags[IsDirectControl]; }
227 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
228 bool isCondCtrl() const { return flags[IsCondControl]; }
229 bool isUncondCtrl() const { return flags[IsUncondControl]; }
230 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
231
232 bool isThreadSync() const { return flags[IsThreadSync]; }
233 bool isSerializing() const { return flags[IsSerializing] ||
234 flags[IsSerializeBefore] ||
235 flags[IsSerializeAfter]; }
236 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
237 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
238 bool isMemBarrier() const { return flags[IsMemBarrier]; }
239 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
240 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
241 bool isQuiesce() const { return flags[IsQuiesce]; }
242 bool isIprAccess() const { return flags[IsIprAccess]; }
243 bool isUnverifiable() const { return flags[IsUnverifiable]; }
244 bool isMacroOp() const { return flags[IsMacroOp]; }
245 bool isMicroOp() const { return flags[IsMicroOp]; }
246 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
247 bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
248 bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
249 //This flag doesn't do anything yet
250 bool isMicroBranch() const { return flags[IsMicroBranch]; }
251 //@}
252
253 /// Operation class. Used to select appropriate function unit in issue.
254 OpClass opClass() const { return _opClass; }
255};
256
257
258// forward declaration
259class StaticInstPtr;
260
261/**
262 * Generic yet ISA-dependent static instruction class.
263 *
264 * This class builds on StaticInstBase, defining fields and interfaces
265 * that are generic across all ISAs but that differ in details
266 * according to the specific ISA being used.
267 */
268class StaticInst : public StaticInstBase
269{
270 public:
271
272 /// Binary machine instruction type.
273 typedef TheISA::MachInst MachInst;
274 /// Binary extended machine instruction type.
275 typedef TheISA::ExtMachInst ExtMachInst;
276 /// Logical register index type.
277 typedef TheISA::RegIndex RegIndex;
278
279 enum {
280 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
281 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
282 };
283
284
285 /// Return logical index (architectural reg num) of i'th destination reg.
286 /// Only the entries from 0 through numDestRegs()-1 are valid.
287 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
288
289 /// Return logical index (architectural reg num) of i'th source reg.
290 /// Only the entries from 0 through numSrcRegs()-1 are valid.
291 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
292
293 /// Pointer to a statically allocated "null" instruction object.
294 /// Used to give eaCompInst() and memAccInst() something to return
295 /// when called on non-memory instructions.
296 static StaticInstPtr nullStaticInstPtr;
297
298 /**
299 * Memory references only: returns "fake" instruction representing
300 * the effective address part of the memory operation. Used to
301 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
302 * just the EA computation.
303 */
304 virtual const
305 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
306
307 /**
308 * Memory references only: returns "fake" instruction representing
309 * the memory access part of the memory operation. Used to
310 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
311 * just the memory access (not the EA computation).
312 */
313 virtual const
314 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
315
316 /// The binary machine instruction.
317 const ExtMachInst machInst;
318
319 protected:
320
321 /// See destRegIdx().
322 RegIndex _destRegIdx[MaxInstDestRegs];
323 /// See srcRegIdx().
324 RegIndex _srcRegIdx[MaxInstSrcRegs];
325
326 /**
327 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
328 * methods. Also useful to readily identify instructions from
329 * within the debugger when #cachedDisassembly has not been
330 * initialized.
331 */
332 const char *mnemonic;
333
334 /**
335 * String representation of disassembly (lazily evaluated via
336 * disassemble()).
337 */
338 mutable std::string *cachedDisassembly;
339
340 /**
341 * Internal function to generate disassembly string.
342 */
343 virtual std::string
344 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
345
346 /// Constructor.
347 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
348 : StaticInstBase(__opClass),
349 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
350 {
351 }
352
353 public:
354
355 virtual ~StaticInst()
356 {
357 if (cachedDisassembly)
358 delete cachedDisassembly;
359 }
360
361/**
362 * The execute() signatures are auto-generated by scons based on the
363 * set of CPU models we are compiling in today.
364 */
365#include "cpu/static_inst_exec_sigs.hh"
366
367 /**
368 * Return the microop that goes with a particular micropc. This should
369 * only be defined/used in macroops which will contain microops
370 */
371 virtual StaticInstPtr fetchMicroOp(MicroPC micropc);
372
373 /**
374 * Return the target address for a PC-relative branch.
375 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
376 * should be true).
377 */
378 virtual Addr branchTarget(Addr branchPC) const
379 {
380 panic("StaticInst::branchTarget() called on instruction "
381 "that is not a PC-relative branch.");
382 M5_DUMMY_RETURN
383 }
384
385 /**
386 * Return the target address for an indirect branch (jump). The
387 * register value is read from the supplied thread context, so
388 * the result is valid only if the thread context is about to
389 * execute the branch in question. Invalid if not an indirect
390 * branch (i.e. isIndirectCtrl() should be true).
391 */
392 virtual Addr branchTarget(ThreadContext *tc) const
393 {
394 panic("StaticInst::branchTarget() called on instruction "
395 "that is not an indirect branch.");
396 }
397 M5_DUMMY_RETURN
398
399 /**
400 * Return true if the instruction is a control transfer, and if so,
401 * return the target address as well.
402 */
403 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
404
405 /**
406 * Return string representation of disassembled instruction.
407 * The default version of this function will call the internal
408 * virtual generateDisassembly() function to get the string,
409 * then cache it in #cachedDisassembly. If the disassembly
410 * should not be cached, this function should be overridden directly.
411 */
412 virtual const std::string &disassemble(Addr pc,
413 const SymbolTable *symtab = 0) const
414 {
415 if (!cachedDisassembly)
416 cachedDisassembly =
417 new std::string(generateDisassembly(pc, symtab));
418
419 return *cachedDisassembly;
420 }
421
422 /// Decoded instruction cache type.
423 /// For now we're using a generic hash_map; this seems to work
424 /// pretty well.
425 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
426
427 /// A cache of decoded instruction objects.
428 static DecodeCache decodeCache;
429
430 /**
431 * Dump some basic stats on the decode cache hash map.
432 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
433 */
434 static void dumpDecodeCacheStats();
435
436 /// Decode a machine instruction.
437 /// @param mach_inst The binary instruction to decode.
438 /// @retval A pointer to the corresponding StaticInst object.
439 //This is defined as inline below.
440 static StaticInstPtr decode(ExtMachInst mach_inst);
441
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "sim/faults.hh"
39#include "base/bitfield.hh"
40#include "base/hashmap.hh"
41#include "base/misc.hh"
42#include "base/refcnt.hh"
43#include "cpu/op_class.hh"
44#include "cpu/o3/dyn_inst.hh"
45#include "sim/faults.hh"
46#include "sim/host.hh"
47
48// forward declarations
49struct AlphaSimpleImpl;
50struct OzoneImpl;
51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56template <class Impl>
57class OzoneDynInst;
58
59class CheckerCPU;
60class FastCPU;
61class AtomicSimpleCPU;
62class TimingSimpleCPU;
63class InorderCPU;
64class SymbolTable;
65
66namespace Trace {
67 class InstRecord;
68}
69
70typedef uint32_t MicroPC;
71
72/**
73 * Base, ISA-independent static instruction class.
74 *
75 * The main component of this class is the vector of flags and the
76 * associated methods for reading them. Any object that can rely
77 * solely on these flags can process instructions without being
78 * recompiled for multiple ISAs.
79 */
80class StaticInstBase : public RefCounted
81{
82 protected:
83
84 /// Set of boolean static instruction properties.
85 ///
86 /// Notes:
87 /// - The IsInteger and IsFloating flags are based on the class of
88 /// registers accessed by the instruction. Although most
89 /// instructions will have exactly one of these two flags set, it
90 /// is possible for an instruction to have neither (e.g., direct
91 /// unconditional branches, memory barriers) or both (e.g., an
92 /// FP/int conversion).
93 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
94 /// will be set.
95 /// - If IsControl is set, then exactly one of IsDirectControl or
96 /// IsIndirect Control will be set, and exactly one of
97 /// IsCondControl or IsUncondControl will be set.
98 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
99 /// implemented as flags since in the current model there's no
100 /// other way for instructions to inject behavior into the
101 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
102 /// model we should be able to get rid of these flags and
103 /// implement this behavior via the execute() methods.
104 ///
105 enum Flags {
106 IsNop, ///< Is a no-op (no effect at all).
107
108 IsInteger, ///< References integer regs.
109 IsFloating, ///< References FP regs.
110
111 IsMemRef, ///< References memory (load, store, or prefetch).
112 IsLoad, ///< Reads from memory (load or prefetch).
113 IsStore, ///< Writes to memory.
114 IsStoreConditional, ///< Store conditional instruction.
115 IsInstPrefetch, ///< Instruction-cache prefetch.
116 IsDataPrefetch, ///< Data-cache prefetch.
117 IsCopy, ///< Fast Cache block copy
118
119 IsControl, ///< Control transfer instruction.
120 IsDirectControl, ///< PC relative control transfer.
121 IsIndirectControl, ///< Register indirect control transfer.
122 IsCondControl, ///< Conditional control transfer.
123 IsUncondControl, ///< Unconditional control transfer.
124 IsCall, ///< Subroutine call.
125 IsReturn, ///< Subroutine return.
126
127 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
128
129 IsThreadSync, ///< Thread synchronization operation.
130
131 IsSerializing, ///< Serializes pipeline: won't execute until all
132 /// older instructions have committed.
133 IsSerializeBefore,
134 IsSerializeAfter,
135 IsMemBarrier, ///< Is a memory barrier
136 IsWriteBarrier, ///< Is a write barrier
137
138 IsNonSpeculative, ///< Should not be executed speculatively
139 IsQuiesce, ///< Is a quiesce instruction
140
141 IsIprAccess, ///< Accesses IPRs
142 IsUnverifiable, ///< Can't be verified by a checker
143
144 //Flags for microcode
145 IsMacroOp, ///< Is a macroop containing microops
146 IsMicroOp, ///< Is a microop
147 IsDelayedCommit, ///< This microop doesn't commit right away
148 IsLastMicroOp, ///< This microop ends a microop sequence
149 IsFirstMicroOp, ///< This microop begins a microop sequence
150 //This flag doesn't do anything yet
151 IsMicroBranch, ///< This microop branches within the microcode for a macroop
152
153 NumFlags
154 };
155
156 /// Flag values for this instruction.
157 std::bitset<NumFlags> flags;
158
159 /// See opClass().
160 OpClass _opClass;
161
162 /// See numSrcRegs().
163 int8_t _numSrcRegs;
164
165 /// See numDestRegs().
166 int8_t _numDestRegs;
167
168 /// The following are used to track physical register usage
169 /// for machines with separate int & FP reg files.
170 //@{
171 int8_t _numFPDestRegs;
172 int8_t _numIntDestRegs;
173 //@}
174
175 /// Constructor.
176 /// It's important to initialize everything here to a sane
177 /// default, since the decoder generally only overrides
178 /// the fields that are meaningful for the particular
179 /// instruction.
180 StaticInstBase(OpClass __opClass)
181 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
182 _numFPDestRegs(0), _numIntDestRegs(0)
183 {
184 }
185
186 public:
187
188 /// @name Register information.
189 /// The sum of numFPDestRegs() and numIntDestRegs() equals
190 /// numDestRegs(). The former two functions are used to track
191 /// physical register usage for machines with separate int & FP
192 /// reg files.
193 //@{
194 /// Number of source registers.
195 int8_t numSrcRegs() const { return _numSrcRegs; }
196 /// Number of destination registers.
197 int8_t numDestRegs() const { return _numDestRegs; }
198 /// Number of floating-point destination regs.
199 int8_t numFPDestRegs() const { return _numFPDestRegs; }
200 /// Number of integer destination regs.
201 int8_t numIntDestRegs() const { return _numIntDestRegs; }
202 //@}
203
204 /// @name Flag accessors.
205 /// These functions are used to access the values of the various
206 /// instruction property flags. See StaticInstBase::Flags for descriptions
207 /// of the individual flags.
208 //@{
209
210 bool isNop() const { return flags[IsNop]; }
211
212 bool isMemRef() const { return flags[IsMemRef]; }
213 bool isLoad() const { return flags[IsLoad]; }
214 bool isStore() const { return flags[IsStore]; }
215 bool isStoreConditional() const { return flags[IsStoreConditional]; }
216 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
217 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
218 bool isCopy() const { return flags[IsCopy];}
219
220 bool isInteger() const { return flags[IsInteger]; }
221 bool isFloating() const { return flags[IsFloating]; }
222
223 bool isControl() const { return flags[IsControl]; }
224 bool isCall() const { return flags[IsCall]; }
225 bool isReturn() const { return flags[IsReturn]; }
226 bool isDirectCtrl() const { return flags[IsDirectControl]; }
227 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
228 bool isCondCtrl() const { return flags[IsCondControl]; }
229 bool isUncondCtrl() const { return flags[IsUncondControl]; }
230 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
231
232 bool isThreadSync() const { return flags[IsThreadSync]; }
233 bool isSerializing() const { return flags[IsSerializing] ||
234 flags[IsSerializeBefore] ||
235 flags[IsSerializeAfter]; }
236 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
237 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
238 bool isMemBarrier() const { return flags[IsMemBarrier]; }
239 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
240 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
241 bool isQuiesce() const { return flags[IsQuiesce]; }
242 bool isIprAccess() const { return flags[IsIprAccess]; }
243 bool isUnverifiable() const { return flags[IsUnverifiable]; }
244 bool isMacroOp() const { return flags[IsMacroOp]; }
245 bool isMicroOp() const { return flags[IsMicroOp]; }
246 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
247 bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
248 bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
249 //This flag doesn't do anything yet
250 bool isMicroBranch() const { return flags[IsMicroBranch]; }
251 //@}
252
253 /// Operation class. Used to select appropriate function unit in issue.
254 OpClass opClass() const { return _opClass; }
255};
256
257
258// forward declaration
259class StaticInstPtr;
260
261/**
262 * Generic yet ISA-dependent static instruction class.
263 *
264 * This class builds on StaticInstBase, defining fields and interfaces
265 * that are generic across all ISAs but that differ in details
266 * according to the specific ISA being used.
267 */
268class StaticInst : public StaticInstBase
269{
270 public:
271
272 /// Binary machine instruction type.
273 typedef TheISA::MachInst MachInst;
274 /// Binary extended machine instruction type.
275 typedef TheISA::ExtMachInst ExtMachInst;
276 /// Logical register index type.
277 typedef TheISA::RegIndex RegIndex;
278
279 enum {
280 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
281 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
282 };
283
284
285 /// Return logical index (architectural reg num) of i'th destination reg.
286 /// Only the entries from 0 through numDestRegs()-1 are valid.
287 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
288
289 /// Return logical index (architectural reg num) of i'th source reg.
290 /// Only the entries from 0 through numSrcRegs()-1 are valid.
291 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
292
293 /// Pointer to a statically allocated "null" instruction object.
294 /// Used to give eaCompInst() and memAccInst() something to return
295 /// when called on non-memory instructions.
296 static StaticInstPtr nullStaticInstPtr;
297
298 /**
299 * Memory references only: returns "fake" instruction representing
300 * the effective address part of the memory operation. Used to
301 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
302 * just the EA computation.
303 */
304 virtual const
305 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
306
307 /**
308 * Memory references only: returns "fake" instruction representing
309 * the memory access part of the memory operation. Used to
310 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
311 * just the memory access (not the EA computation).
312 */
313 virtual const
314 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
315
316 /// The binary machine instruction.
317 const ExtMachInst machInst;
318
319 protected:
320
321 /// See destRegIdx().
322 RegIndex _destRegIdx[MaxInstDestRegs];
323 /// See srcRegIdx().
324 RegIndex _srcRegIdx[MaxInstSrcRegs];
325
326 /**
327 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
328 * methods. Also useful to readily identify instructions from
329 * within the debugger when #cachedDisassembly has not been
330 * initialized.
331 */
332 const char *mnemonic;
333
334 /**
335 * String representation of disassembly (lazily evaluated via
336 * disassemble()).
337 */
338 mutable std::string *cachedDisassembly;
339
340 /**
341 * Internal function to generate disassembly string.
342 */
343 virtual std::string
344 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
345
346 /// Constructor.
347 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
348 : StaticInstBase(__opClass),
349 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
350 {
351 }
352
353 public:
354
355 virtual ~StaticInst()
356 {
357 if (cachedDisassembly)
358 delete cachedDisassembly;
359 }
360
361/**
362 * The execute() signatures are auto-generated by scons based on the
363 * set of CPU models we are compiling in today.
364 */
365#include "cpu/static_inst_exec_sigs.hh"
366
367 /**
368 * Return the microop that goes with a particular micropc. This should
369 * only be defined/used in macroops which will contain microops
370 */
371 virtual StaticInstPtr fetchMicroOp(MicroPC micropc);
372
373 /**
374 * Return the target address for a PC-relative branch.
375 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
376 * should be true).
377 */
378 virtual Addr branchTarget(Addr branchPC) const
379 {
380 panic("StaticInst::branchTarget() called on instruction "
381 "that is not a PC-relative branch.");
382 M5_DUMMY_RETURN
383 }
384
385 /**
386 * Return the target address for an indirect branch (jump). The
387 * register value is read from the supplied thread context, so
388 * the result is valid only if the thread context is about to
389 * execute the branch in question. Invalid if not an indirect
390 * branch (i.e. isIndirectCtrl() should be true).
391 */
392 virtual Addr branchTarget(ThreadContext *tc) const
393 {
394 panic("StaticInst::branchTarget() called on instruction "
395 "that is not an indirect branch.");
396 }
397 M5_DUMMY_RETURN
398
399 /**
400 * Return true if the instruction is a control transfer, and if so,
401 * return the target address as well.
402 */
403 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
404
405 /**
406 * Return string representation of disassembled instruction.
407 * The default version of this function will call the internal
408 * virtual generateDisassembly() function to get the string,
409 * then cache it in #cachedDisassembly. If the disassembly
410 * should not be cached, this function should be overridden directly.
411 */
412 virtual const std::string &disassemble(Addr pc,
413 const SymbolTable *symtab = 0) const
414 {
415 if (!cachedDisassembly)
416 cachedDisassembly =
417 new std::string(generateDisassembly(pc, symtab));
418
419 return *cachedDisassembly;
420 }
421
422 /// Decoded instruction cache type.
423 /// For now we're using a generic hash_map; this seems to work
424 /// pretty well.
425 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
426
427 /// A cache of decoded instruction objects.
428 static DecodeCache decodeCache;
429
430 /**
431 * Dump some basic stats on the decode cache hash map.
432 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
433 */
434 static void dumpDecodeCacheStats();
435
436 /// Decode a machine instruction.
437 /// @param mach_inst The binary instruction to decode.
438 /// @retval A pointer to the corresponding StaticInst object.
439 //This is defined as inline below.
440 static StaticInstPtr decode(ExtMachInst mach_inst);
441
|