1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Steve Reinhardt 30 */ 31 32#ifndef __CPU_STATIC_INST_HH__ 33#define __CPU_STATIC_INST_HH__ 34 35#include <bitset> 36#include <string> 37 38#include "arch/registers.hh" 39#include "arch/types.hh" 40#include "base/misc.hh" 41#include "base/refcnt.hh" 42#include "base/types.hh" 43#include "config/the_isa.hh" 44#include "cpu/op_class.hh"
| 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Steve Reinhardt 30 */ 31 32#ifndef __CPU_STATIC_INST_HH__ 33#define __CPU_STATIC_INST_HH__ 34 35#include <bitset> 36#include <string> 37 38#include "arch/registers.hh" 39#include "arch/types.hh" 40#include "base/misc.hh" 41#include "base/refcnt.hh" 42#include "base/types.hh" 43#include "config/the_isa.hh" 44#include "cpu/op_class.hh"
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| 45#include "cpu/reg_class.hh"
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45#include "cpu/static_inst_fwd.hh" 46#include "cpu/thread_context.hh" 47#include "enums/StaticInstFlags.hh" 48 49// forward declarations 50class Packet; 51 52class ExecContext; 53 54class SymbolTable; 55 56namespace Trace { 57 class InstRecord; 58} 59 60/** 61 * Base, ISA-independent static instruction class. 62 * 63 * The main component of this class is the vector of flags and the 64 * associated methods for reading them. Any object that can rely 65 * solely on these flags can process instructions without being 66 * recompiled for multiple ISAs. 67 */ 68class StaticInst : public RefCounted, public StaticInstFlags 69{ 70 public: 71 /// Binary extended machine instruction type. 72 typedef TheISA::ExtMachInst ExtMachInst;
| 46#include "cpu/static_inst_fwd.hh" 47#include "cpu/thread_context.hh" 48#include "enums/StaticInstFlags.hh" 49 50// forward declarations 51class Packet; 52 53class ExecContext; 54 55class SymbolTable; 56 57namespace Trace { 58 class InstRecord; 59} 60 61/** 62 * Base, ISA-independent static instruction class. 63 * 64 * The main component of this class is the vector of flags and the 65 * associated methods for reading them. Any object that can rely 66 * solely on these flags can process instructions without being 67 * recompiled for multiple ISAs. 68 */ 69class StaticInst : public RefCounted, public StaticInstFlags 70{ 71 public: 72 /// Binary extended machine instruction type. 73 typedef TheISA::ExtMachInst ExtMachInst;
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73 /// Logical register index type. 74 typedef TheISA::RegIndex RegIndex;
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75 76 enum { 77 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 78 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 79 }; 80 81 protected: 82 83 /// Flag values for this instruction. 84 std::bitset<Num_Flags> flags; 85 86 /// See opClass(). 87 OpClass _opClass; 88 89 /// See numSrcRegs(). 90 int8_t _numSrcRegs; 91 92 /// See numDestRegs(). 93 int8_t _numDestRegs; 94 95 /// The following are used to track physical register usage 96 /// for machines with separate int & FP reg files. 97 //@{ 98 int8_t _numFPDestRegs; 99 int8_t _numIntDestRegs; 100 int8_t _numCCDestRegs; 101 //@} 102 103 public: 104 105 /// @name Register information. 106 /// The sum of numFPDestRegs() and numIntDestRegs() equals 107 /// numDestRegs(). The former two functions are used to track 108 /// physical register usage for machines with separate int & FP 109 /// reg files. 110 //@{ 111 /// Number of source registers. 112 int8_t numSrcRegs() const { return _numSrcRegs; } 113 /// Number of destination registers. 114 int8_t numDestRegs() const { return _numDestRegs; } 115 /// Number of floating-point destination regs. 116 int8_t numFPDestRegs() const { return _numFPDestRegs; } 117 /// Number of integer destination regs. 118 int8_t numIntDestRegs() const { return _numIntDestRegs; } 119 //@} 120 /// Number of coprocesor destination regs. 121 int8_t numCCDestRegs() const { return _numCCDestRegs; } 122 //@} 123 124 /// @name Flag accessors. 125 /// These functions are used to access the values of the various 126 /// instruction property flags. See StaticInst::Flags for descriptions 127 /// of the individual flags. 128 //@{ 129 130 bool isNop() const { return flags[IsNop]; } 131 132 bool isMemRef() const { return flags[IsMemRef]; } 133 bool isLoad() const { return flags[IsLoad]; } 134 bool isStore() const { return flags[IsStore]; } 135 bool isStoreConditional() const { return flags[IsStoreConditional]; } 136 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 137 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 138 bool isPrefetch() const { return isInstPrefetch() || 139 isDataPrefetch(); } 140 141 bool isInteger() const { return flags[IsInteger]; } 142 bool isFloating() const { return flags[IsFloating]; } 143 bool isCC() const { return flags[IsCC]; } 144 145 bool isControl() const { return flags[IsControl]; } 146 bool isCall() const { return flags[IsCall]; } 147 bool isReturn() const { return flags[IsReturn]; } 148 bool isDirectCtrl() const { return flags[IsDirectControl]; } 149 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 150 bool isCondCtrl() const { return flags[IsCondControl]; } 151 bool isUncondCtrl() const { return flags[IsUncondControl]; } 152 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 153 154 bool isThreadSync() const { return flags[IsThreadSync]; } 155 bool isSerializing() const { return flags[IsSerializing] || 156 flags[IsSerializeBefore] || 157 flags[IsSerializeAfter]; } 158 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 159 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 160 bool isSquashAfter() const { return flags[IsSquashAfter]; } 161 bool isMemBarrier() const { return flags[IsMemBarrier]; } 162 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 163 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 164 bool isQuiesce() const { return flags[IsQuiesce]; } 165 bool isIprAccess() const { return flags[IsIprAccess]; } 166 bool isUnverifiable() const { return flags[IsUnverifiable]; } 167 bool isSyscall() const { return flags[IsSyscall]; } 168 bool isMacroop() const { return flags[IsMacroop]; } 169 bool isMicroop() const { return flags[IsMicroop]; } 170 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 171 bool isLastMicroop() const { return flags[IsLastMicroop]; } 172 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 173 //This flag doesn't do anything yet 174 bool isMicroBranch() const { return flags[IsMicroBranch]; } 175 //@} 176 177 void setFirstMicroop() { flags[IsFirstMicroop] = true; } 178 void setLastMicroop() { flags[IsLastMicroop] = true; } 179 void setDelayedCommit() { flags[IsDelayedCommit] = true; } 180 void setFlag(Flags f) { flags[f] = true; } 181 182 /// Operation class. Used to select appropriate function unit in issue. 183 OpClass opClass() const { return _opClass; } 184 185 186 /// Return logical index (architectural reg num) of i'th destination reg. 187 /// Only the entries from 0 through numDestRegs()-1 are valid.
| 74 75 enum { 76 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 77 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 78 }; 79 80 protected: 81 82 /// Flag values for this instruction. 83 std::bitset<Num_Flags> flags; 84 85 /// See opClass(). 86 OpClass _opClass; 87 88 /// See numSrcRegs(). 89 int8_t _numSrcRegs; 90 91 /// See numDestRegs(). 92 int8_t _numDestRegs; 93 94 /// The following are used to track physical register usage 95 /// for machines with separate int & FP reg files. 96 //@{ 97 int8_t _numFPDestRegs; 98 int8_t _numIntDestRegs; 99 int8_t _numCCDestRegs; 100 //@} 101 102 public: 103 104 /// @name Register information. 105 /// The sum of numFPDestRegs() and numIntDestRegs() equals 106 /// numDestRegs(). The former two functions are used to track 107 /// physical register usage for machines with separate int & FP 108 /// reg files. 109 //@{ 110 /// Number of source registers. 111 int8_t numSrcRegs() const { return _numSrcRegs; } 112 /// Number of destination registers. 113 int8_t numDestRegs() const { return _numDestRegs; } 114 /// Number of floating-point destination regs. 115 int8_t numFPDestRegs() const { return _numFPDestRegs; } 116 /// Number of integer destination regs. 117 int8_t numIntDestRegs() const { return _numIntDestRegs; } 118 //@} 119 /// Number of coprocesor destination regs. 120 int8_t numCCDestRegs() const { return _numCCDestRegs; } 121 //@} 122 123 /// @name Flag accessors. 124 /// These functions are used to access the values of the various 125 /// instruction property flags. See StaticInst::Flags for descriptions 126 /// of the individual flags. 127 //@{ 128 129 bool isNop() const { return flags[IsNop]; } 130 131 bool isMemRef() const { return flags[IsMemRef]; } 132 bool isLoad() const { return flags[IsLoad]; } 133 bool isStore() const { return flags[IsStore]; } 134 bool isStoreConditional() const { return flags[IsStoreConditional]; } 135 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 136 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 137 bool isPrefetch() const { return isInstPrefetch() || 138 isDataPrefetch(); } 139 140 bool isInteger() const { return flags[IsInteger]; } 141 bool isFloating() const { return flags[IsFloating]; } 142 bool isCC() const { return flags[IsCC]; } 143 144 bool isControl() const { return flags[IsControl]; } 145 bool isCall() const { return flags[IsCall]; } 146 bool isReturn() const { return flags[IsReturn]; } 147 bool isDirectCtrl() const { return flags[IsDirectControl]; } 148 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 149 bool isCondCtrl() const { return flags[IsCondControl]; } 150 bool isUncondCtrl() const { return flags[IsUncondControl]; } 151 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 152 153 bool isThreadSync() const { return flags[IsThreadSync]; } 154 bool isSerializing() const { return flags[IsSerializing] || 155 flags[IsSerializeBefore] || 156 flags[IsSerializeAfter]; } 157 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 158 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 159 bool isSquashAfter() const { return flags[IsSquashAfter]; } 160 bool isMemBarrier() const { return flags[IsMemBarrier]; } 161 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 162 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 163 bool isQuiesce() const { return flags[IsQuiesce]; } 164 bool isIprAccess() const { return flags[IsIprAccess]; } 165 bool isUnverifiable() const { return flags[IsUnverifiable]; } 166 bool isSyscall() const { return flags[IsSyscall]; } 167 bool isMacroop() const { return flags[IsMacroop]; } 168 bool isMicroop() const { return flags[IsMicroop]; } 169 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 170 bool isLastMicroop() const { return flags[IsLastMicroop]; } 171 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 172 //This flag doesn't do anything yet 173 bool isMicroBranch() const { return flags[IsMicroBranch]; } 174 //@} 175 176 void setFirstMicroop() { flags[IsFirstMicroop] = true; } 177 void setLastMicroop() { flags[IsLastMicroop] = true; } 178 void setDelayedCommit() { flags[IsDelayedCommit] = true; } 179 void setFlag(Flags f) { flags[f] = true; } 180 181 /// Operation class. Used to select appropriate function unit in issue. 182 OpClass opClass() const { return _opClass; } 183 184 185 /// Return logical index (architectural reg num) of i'th destination reg. 186 /// Only the entries from 0 through numDestRegs()-1 are valid.
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188 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
| 187 RegId destRegIdx(int i) const { return _destRegIdx[i]; }
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189 190 /// Return logical index (architectural reg num) of i'th source reg. 191 /// Only the entries from 0 through numSrcRegs()-1 are valid.
| 188 189 /// Return logical index (architectural reg num) of i'th source reg. 190 /// Only the entries from 0 through numSrcRegs()-1 are valid.
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192 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
| 191 RegId srcRegIdx(int i) const { return _srcRegIdx[i]; }
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193 194 /// Pointer to a statically allocated "null" instruction object. 195 /// Used to give eaCompInst() and memAccInst() something to return 196 /// when called on non-memory instructions. 197 static StaticInstPtr nullStaticInstPtr; 198 199 /** 200 * Memory references only: returns "fake" instruction representing 201 * the effective address part of the memory operation. Used to 202 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 203 * just the EA computation. 204 */ 205 virtual const 206 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 207 208 /** 209 * Memory references only: returns "fake" instruction representing 210 * the memory access part of the memory operation. Used to 211 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 212 * just the memory access (not the EA computation). 213 */ 214 virtual const 215 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 216 217 /// The binary machine instruction. 218 const ExtMachInst machInst; 219 220 protected: 221 222 /// See destRegIdx().
| 192 193 /// Pointer to a statically allocated "null" instruction object. 194 /// Used to give eaCompInst() and memAccInst() something to return 195 /// when called on non-memory instructions. 196 static StaticInstPtr nullStaticInstPtr; 197 198 /** 199 * Memory references only: returns "fake" instruction representing 200 * the effective address part of the memory operation. Used to 201 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 202 * just the EA computation. 203 */ 204 virtual const 205 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 206 207 /** 208 * Memory references only: returns "fake" instruction representing 209 * the memory access part of the memory operation. Used to 210 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 211 * just the memory access (not the EA computation). 212 */ 213 virtual const 214 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 215 216 /// The binary machine instruction. 217 const ExtMachInst machInst; 218 219 protected: 220 221 /// See destRegIdx().
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223 RegIndex _destRegIdx[MaxInstDestRegs];
| 222 RegId _destRegIdx[MaxInstDestRegs];
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224 /// See srcRegIdx().
| 223 /// See srcRegIdx().
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225 RegIndex _srcRegIdx[MaxInstSrcRegs];
| 224 RegId _srcRegIdx[MaxInstSrcRegs];
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226 227 /** 228 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 229 * methods. Also useful to readily identify instructions from 230 * within the debugger when #cachedDisassembly has not been 231 * initialized. 232 */ 233 const char *mnemonic; 234 235 /** 236 * String representation of disassembly (lazily evaluated via 237 * disassemble()). 238 */ 239 mutable std::string *cachedDisassembly; 240 241 /** 242 * Internal function to generate disassembly string. 243 */ 244 virtual std::string 245 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 246 247 /// Constructor. 248 /// It's important to initialize everything here to a sane 249 /// default, since the decoder generally only overrides 250 /// the fields that are meaningful for the particular 251 /// instruction. 252 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 253 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 254 _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0), 255 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 256 { } 257 258 public: 259 virtual ~StaticInst(); 260 261 virtual Fault execute(ExecContext *xc, 262 Trace::InstRecord *traceData) const = 0; 263 virtual Fault eaComp(ExecContext *xc, 264 Trace::InstRecord *traceData) const 265 { 266 panic("eaComp not defined!"); 267 } 268 269 virtual Fault initiateAcc(ExecContext *xc, 270 Trace::InstRecord *traceData) const 271 { 272 panic("initiateAcc not defined!"); 273 } 274 275 virtual Fault completeAcc(Packet *pkt, ExecContext *xc, 276 Trace::InstRecord *traceData) const 277 { 278 panic("completeAcc not defined!"); 279 } 280 281 virtual void advancePC(TheISA::PCState &pcState) const = 0; 282 283 /** 284 * Return the microop that goes with a particular micropc. This should 285 * only be defined/used in macroops which will contain microops 286 */ 287 virtual StaticInstPtr fetchMicroop(MicroPC upc) const; 288 289 /** 290 * Return the target address for a PC-relative branch. 291 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 292 * should be true). 293 */ 294 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const; 295 296 /** 297 * Return the target address for an indirect branch (jump). The 298 * register value is read from the supplied thread context, so 299 * the result is valid only if the thread context is about to 300 * execute the branch in question. Invalid if not an indirect 301 * branch (i.e. isIndirectCtrl() should be true). 302 */ 303 virtual TheISA::PCState branchTarget(ThreadContext *tc) const; 304 305 /** 306 * Return true if the instruction is a control transfer, and if so, 307 * return the target address as well. 308 */ 309 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 310 TheISA::PCState &tgt) const; 311 312 /** 313 * Return string representation of disassembled instruction. 314 * The default version of this function will call the internal 315 * virtual generateDisassembly() function to get the string, 316 * then cache it in #cachedDisassembly. If the disassembly 317 * should not be cached, this function should be overridden directly. 318 */ 319 virtual const std::string &disassemble(Addr pc, 320 const SymbolTable *symtab = 0) const; 321 322 /** 323 * Print a separator separated list of this instruction's set flag 324 * names on the given stream. 325 */ 326 void printFlags(std::ostream &outs, const std::string &separator) const; 327 328 /// Return name of machine instruction 329 std::string getName() { return mnemonic; } 330}; 331 332#endif // __CPU_STATIC_INST_HH__
| 225 226 /** 227 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 228 * methods. Also useful to readily identify instructions from 229 * within the debugger when #cachedDisassembly has not been 230 * initialized. 231 */ 232 const char *mnemonic; 233 234 /** 235 * String representation of disassembly (lazily evaluated via 236 * disassemble()). 237 */ 238 mutable std::string *cachedDisassembly; 239 240 /** 241 * Internal function to generate disassembly string. 242 */ 243 virtual std::string 244 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 245 246 /// Constructor. 247 /// It's important to initialize everything here to a sane 248 /// default, since the decoder generally only overrides 249 /// the fields that are meaningful for the particular 250 /// instruction. 251 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 252 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 253 _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0), 254 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 255 { } 256 257 public: 258 virtual ~StaticInst(); 259 260 virtual Fault execute(ExecContext *xc, 261 Trace::InstRecord *traceData) const = 0; 262 virtual Fault eaComp(ExecContext *xc, 263 Trace::InstRecord *traceData) const 264 { 265 panic("eaComp not defined!"); 266 } 267 268 virtual Fault initiateAcc(ExecContext *xc, 269 Trace::InstRecord *traceData) const 270 { 271 panic("initiateAcc not defined!"); 272 } 273 274 virtual Fault completeAcc(Packet *pkt, ExecContext *xc, 275 Trace::InstRecord *traceData) const 276 { 277 panic("completeAcc not defined!"); 278 } 279 280 virtual void advancePC(TheISA::PCState &pcState) const = 0; 281 282 /** 283 * Return the microop that goes with a particular micropc. This should 284 * only be defined/used in macroops which will contain microops 285 */ 286 virtual StaticInstPtr fetchMicroop(MicroPC upc) const; 287 288 /** 289 * Return the target address for a PC-relative branch. 290 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 291 * should be true). 292 */ 293 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const; 294 295 /** 296 * Return the target address for an indirect branch (jump). The 297 * register value is read from the supplied thread context, so 298 * the result is valid only if the thread context is about to 299 * execute the branch in question. Invalid if not an indirect 300 * branch (i.e. isIndirectCtrl() should be true). 301 */ 302 virtual TheISA::PCState branchTarget(ThreadContext *tc) const; 303 304 /** 305 * Return true if the instruction is a control transfer, and if so, 306 * return the target address as well. 307 */ 308 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 309 TheISA::PCState &tgt) const; 310 311 /** 312 * Return string representation of disassembled instruction. 313 * The default version of this function will call the internal 314 * virtual generateDisassembly() function to get the string, 315 * then cache it in #cachedDisassembly. If the disassembly 316 * should not be cached, this function should be overridden directly. 317 */ 318 virtual const std::string &disassemble(Addr pc, 319 const SymbolTable *symtab = 0) const; 320 321 /** 322 * Print a separator separated list of this instruction's set flag 323 * names on the given stream. 324 */ 325 void printFlags(std::ostream &outs, const std::string &separator) const; 326 327 /// Return name of machine instruction 328 std::string getName() { return mnemonic; } 329}; 330 331#endif // __CPU_STATIC_INST_HH__
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