1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/registers.hh"
38#include "arch/types.hh"
39#include "base/misc.hh"
40#include "base/refcnt.hh"
41#include "base/types.hh"
42#include "config/the_isa.hh"
43#include "cpu/op_class.hh"
44#include "cpu/static_inst_fwd.hh"
45#include "sim/fault_fwd.hh"
46
47// forward declarations
48struct AlphaSimpleImpl;
49struct OzoneImpl;
50struct SimpleImpl;
51class ThreadContext;
52class DynInst;
53class Packet;
54
55struct O3CPUImpl;
56template <class Impl> class BaseO3DynInst;
57typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
58template <class Impl> class OzoneDynInst;
59class InOrderDynInst;
60
61class CheckerCPU;
62class FastCPU;
63class AtomicSimpleCPU;
64class TimingSimpleCPU;
65class InorderCPU;
66class SymbolTable;
67
68namespace Trace {
69 class InstRecord;
70}
71
72/**
73 * Base, ISA-independent static instruction class.
74 *
75 * The main component of this class is the vector of flags and the
76 * associated methods for reading them. Any object that can rely
77 * solely on these flags can process instructions without being
78 * recompiled for multiple ISAs.
79 */
80class StaticInst : public RefCounted
81{
82 public:
83 /// Binary extended machine instruction type.
84 typedef TheISA::ExtMachInst ExtMachInst;
85 /// Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87
88 enum {
89 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
90 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
91 };
92
93 /// Set of boolean static instruction properties.
94 ///
95 /// Notes:
96 /// - The IsInteger and IsFloating flags are based on the class of
97 /// registers accessed by the instruction. Although most
98 /// instructions will have exactly one of these two flags set, it
99 /// is possible for an instruction to have neither (e.g., direct
100 /// unconditional branches, memory barriers) or both (e.g., an
101 /// FP/int conversion).
102 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
103 /// will be set.
104 /// - If IsControl is set, then exactly one of IsDirectControl or
105 /// IsIndirect Control will be set, and exactly one of
106 /// IsCondControl or IsUncondControl will be set.
107 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
108 /// implemented as flags since in the current model there's no
109 /// other way for instructions to inject behavior into the
110 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
111 /// model we should be able to get rid of these flags and
112 /// implement this behavior via the execute() methods.
113 ///
114 enum Flags {
115 IsNop, ///< Is a no-op (no effect at all).
116
117 IsInteger, ///< References integer regs.
118 IsFloating, ///< References FP regs.
119
120 IsMemRef, ///< References memory (load, store, or prefetch).
121 IsLoad, ///< Reads from memory (load or prefetch).
122 IsStore, ///< Writes to memory.
123 IsStoreConditional, ///< Store conditional instruction.
124 IsIndexed, ///< Accesses memory with an indexed address computation
125 IsInstPrefetch, ///< Instruction-cache prefetch.
126 IsDataPrefetch, ///< Data-cache prefetch.
127
128 IsControl, ///< Control transfer instruction.
129 IsDirectControl, ///< PC relative control transfer.
130 IsIndirectControl, ///< Register indirect control transfer.
131 IsCondControl, ///< Conditional control transfer.
132 IsUncondControl, ///< Unconditional control transfer.
133 IsCall, ///< Subroutine call.
134 IsReturn, ///< Subroutine return.
135
136 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
137
138 IsThreadSync, ///< Thread synchronization operation.
139
140 IsSerializing, ///< Serializes pipeline: won't execute until all
141 /// older instructions have committed.
142 IsSerializeBefore,
143 IsSerializeAfter,
144 IsMemBarrier, ///< Is a memory barrier
145 IsWriteBarrier, ///< Is a write barrier
146 IsReadBarrier, ///< Is a read barrier
147 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
148
149 IsNonSpeculative, ///< Should not be executed speculatively
150 IsQuiesce, ///< Is a quiesce instruction
151
152 IsIprAccess, ///< Accesses IPRs
153 IsUnverifiable, ///< Can't be verified by a checker
154
155 IsSyscall, ///< Causes a system call to be emulated in syscall
156 /// emulation mode.
157
158 //Flags for microcode
159 IsMacroop, ///< Is a macroop containing microops
160 IsMicroop, ///< Is a microop
161 IsDelayedCommit, ///< This microop doesn't commit right away
162 IsLastMicroop, ///< This microop ends a microop sequence
163 IsFirstMicroop, ///< This microop begins a microop sequence
164 //This flag doesn't do anything yet
165 IsMicroBranch, ///< This microop branches within the microcode for a macroop
166 IsDspOp,
167 IsSquashAfter, ///< Squash all uncommitted state after executed
168 NumFlags
169 };
170
171 protected:
172
173 /// Flag values for this instruction.
174 std::bitset<NumFlags> flags;
175
176 /// See opClass().
177 OpClass _opClass;
178
179 /// See numSrcRegs().
180 int8_t _numSrcRegs;
181
182 /// See numDestRegs().
183 int8_t _numDestRegs;
184
185 /// The following are used to track physical register usage
186 /// for machines with separate int & FP reg files.
187 //@{
188 int8_t _numFPDestRegs;
189 int8_t _numIntDestRegs;
190 //@}
191
192 public:
193
194 /// @name Register information.
195 /// The sum of numFPDestRegs() and numIntDestRegs() equals
196 /// numDestRegs(). The former two functions are used to track
197 /// physical register usage for machines with separate int & FP
198 /// reg files.
199 //@{
200 /// Number of source registers.
201 int8_t numSrcRegs() const { return _numSrcRegs; }
202 /// Number of destination registers.
203 int8_t numDestRegs() const { return _numDestRegs; }
204 /// Number of floating-point destination regs.
205 int8_t numFPDestRegs() const { return _numFPDestRegs; }
206 /// Number of integer destination regs.
207 int8_t numIntDestRegs() const { return _numIntDestRegs; }
208 //@}
209
210 /// @name Flag accessors.
211 /// These functions are used to access the values of the various
212 /// instruction property flags. See StaticInst::Flags for descriptions
213 /// of the individual flags.
214 //@{
215
216 bool isNop() const { return flags[IsNop]; }
217
218 bool isMemRef() const { return flags[IsMemRef]; }
219 bool isLoad() const { return flags[IsLoad]; }
220 bool isStore() const { return flags[IsStore]; }
221 bool isStoreConditional() const { return flags[IsStoreConditional]; }
222 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
223 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
224 bool isPrefetch() const { return isInstPrefetch() ||
225 isDataPrefetch(); }
226
227 bool isInteger() const { return flags[IsInteger]; }
228 bool isFloating() const { return flags[IsFloating]; }
229
230 bool isControl() const { return flags[IsControl]; }
231 bool isCall() const { return flags[IsCall]; }
232 bool isReturn() const { return flags[IsReturn]; }
233 bool isDirectCtrl() const { return flags[IsDirectControl]; }
234 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
235 bool isCondCtrl() const { return flags[IsCondControl]; }
236 bool isUncondCtrl() const { return flags[IsUncondControl]; }
237 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
238
239 bool isThreadSync() const { return flags[IsThreadSync]; }
240 bool isSerializing() const { return flags[IsSerializing] ||
241 flags[IsSerializeBefore] ||
242 flags[IsSerializeAfter]; }
243 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
244 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
245 bool isSquashAfter() const { return flags[IsSquashAfter]; }
246 bool isMemBarrier() const { return flags[IsMemBarrier]; }
247 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
248 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
249 bool isQuiesce() const { return flags[IsQuiesce]; }
250 bool isIprAccess() const { return flags[IsIprAccess]; }
251 bool isUnverifiable() const { return flags[IsUnverifiable]; }
252 bool isSyscall() const { return flags[IsSyscall]; }
253 bool isMacroop() const { return flags[IsMacroop]; }
254 bool isMicroop() const { return flags[IsMicroop]; }
255 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
256 bool isLastMicroop() const { return flags[IsLastMicroop]; }
257 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
258 //This flag doesn't do anything yet
259 bool isMicroBranch() const { return flags[IsMicroBranch]; }
260 //@}
261
262 void setLastMicroop() { flags[IsLastMicroop] = true; }
263 void setDelayedCommit() { flags[IsDelayedCommit] = true; }
264 void setFlag(Flags f) { flags[f] = true; }
265
266 /// Operation class. Used to select appropriate function unit in issue.
267 OpClass opClass() const { return _opClass; }
268
269
270 /// Return logical index (architectural reg num) of i'th destination reg.
271 /// Only the entries from 0 through numDestRegs()-1 are valid.
272 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
273
274 /// Return logical index (architectural reg num) of i'th source reg.
275 /// Only the entries from 0 through numSrcRegs()-1 are valid.
276 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
277
278 /// Pointer to a statically allocated "null" instruction object.
279 /// Used to give eaCompInst() and memAccInst() something to return
280 /// when called on non-memory instructions.
281 static StaticInstPtr nullStaticInstPtr;
282
283 /**
284 * Memory references only: returns "fake" instruction representing
285 * the effective address part of the memory operation. Used to
286 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
287 * just the EA computation.
288 */
289 virtual const
290 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
291
292 /**
293 * Memory references only: returns "fake" instruction representing
294 * the memory access part of the memory operation. Used to
295 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
296 * just the memory access (not the EA computation).
297 */
298 virtual const
299 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
300
301 /// The binary machine instruction.
302 const ExtMachInst machInst;
303
304 protected:
305
306 /// See destRegIdx().
307 RegIndex _destRegIdx[MaxInstDestRegs];
308 /// See srcRegIdx().
309 RegIndex _srcRegIdx[MaxInstSrcRegs];
310
311 /**
312 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
313 * methods. Also useful to readily identify instructions from
314 * within the debugger when #cachedDisassembly has not been
315 * initialized.
316 */
317 const char *mnemonic;
318
319 /**
320 * String representation of disassembly (lazily evaluated via
321 * disassemble()).
322 */
323 mutable std::string *cachedDisassembly;
324
325 /**
326 * Internal function to generate disassembly string.
327 */
328 virtual std::string
329 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
330
331 /// Constructor.
332 /// It's important to initialize everything here to a sane
333 /// default, since the decoder generally only overrides
334 /// the fields that are meaningful for the particular
335 /// instruction.
336 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
337 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
338 _numFPDestRegs(0), _numIntDestRegs(0),
339 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
340 { }
341
342 public:
343 virtual ~StaticInst();
344
345/**
346 * The execute() signatures are auto-generated by scons based on the
347 * set of CPU models we are compiling in today.
348 */
349#include "cpu/static_inst_exec_sigs.hh"
350
351 virtual void advancePC(TheISA::PCState &pcState) const = 0;
352
353 /**
354 * Return the microop that goes with a particular micropc. This should
355 * only be defined/used in macroops which will contain microops
356 */
357 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
358
359 /**
360 * Return the target address for a PC-relative branch.
361 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
362 * should be true).
363 */
364 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
365
366 /**
367 * Return the target address for an indirect branch (jump). The
368 * register value is read from the supplied thread context, so
369 * the result is valid only if the thread context is about to
370 * execute the branch in question. Invalid if not an indirect
371 * branch (i.e. isIndirectCtrl() should be true).
372 */
373 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
374
375 /**
376 * Return true if the instruction is a control transfer, and if so,
377 * return the target address as well.
378 */
379 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
380 TheISA::PCState &tgt) const;
381
382 /**
383 * Return string representation of disassembled instruction.
384 * The default version of this function will call the internal
385 * virtual generateDisassembly() function to get the string,
386 * then cache it in #cachedDisassembly. If the disassembly
387 * should not be cached, this function should be overridden directly.
388 */
389 virtual const std::string &disassemble(Addr pc,
390 const SymbolTable *symtab = 0) const;
391
392 /// Return name of machine instruction
393 std::string getName() { return mnemonic; }
394};
395
396#endif // __CPU_STATIC_INST_HH__