1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "arch/utility.hh"
39#include "sim/faults.hh"
40#include "base/bitfield.hh"
41#include "base/hashmap.hh"
42#include "base/misc.hh"
43#include "base/refcnt.hh"
44#include "cpu/op_class.hh"
45#include "cpu/o3/dyn_inst_decl.hh"
46#include "sim/faults.hh"
47#include "sim/host.hh"
48
49// forward declarations
50struct AlphaSimpleImpl;
51struct OzoneImpl;
52struct SimpleImpl;
53class ThreadContext;
54class DynInst;
55class Packet;
56
57template <class Impl>
58class OzoneDynInst;
59
60class CheckerCPU;
61class FastCPU;
62class AtomicSimpleCPU;
63class TimingSimpleCPU;
64class InorderCPU;
65class SymbolTable;
66class AddrDecodePage;
67
68namespace Trace {
69 class InstRecord;
70}
71
72typedef uint32_t MicroPC;
73
74/**
75 * Base, ISA-independent static instruction class.
76 *
77 * The main component of this class is the vector of flags and the
78 * associated methods for reading them. Any object that can rely
79 * solely on these flags can process instructions without being
80 * recompiled for multiple ISAs.
81 */
82class StaticInstBase : public RefCounted
83{
84 protected:
85
86 /// Set of boolean static instruction properties.
87 ///
88 /// Notes:
89 /// - The IsInteger and IsFloating flags are based on the class of
90 /// registers accessed by the instruction. Although most
91 /// instructions will have exactly one of these two flags set, it
92 /// is possible for an instruction to have neither (e.g., direct
93 /// unconditional branches, memory barriers) or both (e.g., an
94 /// FP/int conversion).
95 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
96 /// will be set.
97 /// - If IsControl is set, then exactly one of IsDirectControl or
98 /// IsIndirect Control will be set, and exactly one of
99 /// IsCondControl or IsUncondControl will be set.
100 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
101 /// implemented as flags since in the current model there's no
102 /// other way for instructions to inject behavior into the
103 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
104 /// model we should be able to get rid of these flags and
105 /// implement this behavior via the execute() methods.
106 ///
107 enum Flags {
108 IsNop, ///< Is a no-op (no effect at all).
109
110 IsInteger, ///< References integer regs.
111 IsFloating, ///< References FP regs.
112
113 IsMemRef, ///< References memory (load, store, or prefetch).
114 IsLoad, ///< Reads from memory (load or prefetch).
115 IsStore, ///< Writes to memory.
116 IsStoreConditional, ///< Store conditional instruction.
117 IsIndexed, ///< Accesses memory with an indexed address computation
118 IsInstPrefetch, ///< Instruction-cache prefetch.
119 IsDataPrefetch, ///< Data-cache prefetch.
120 IsCopy, ///< Fast Cache block copy
121
122 IsControl, ///< Control transfer instruction.
123 IsDirectControl, ///< PC relative control transfer.
124 IsIndirectControl, ///< Register indirect control transfer.
125 IsCondControl, ///< Conditional control transfer.
126 IsUncondControl, ///< Unconditional control transfer.
127 IsCall, ///< Subroutine call.
128 IsReturn, ///< Subroutine return.
129
130 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
131
132 IsThreadSync, ///< Thread synchronization operation.
133
134 IsSerializing, ///< Serializes pipeline: won't execute until all
135 /// older instructions have committed.
136 IsSerializeBefore,
137 IsSerializeAfter,
138 IsMemBarrier, ///< Is a memory barrier
139 IsWriteBarrier, ///< Is a write barrier
140 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
141
142 IsNonSpeculative, ///< Should not be executed speculatively
143 IsQuiesce, ///< Is a quiesce instruction
144
145 IsIprAccess, ///< Accesses IPRs
146 IsUnverifiable, ///< Can't be verified by a checker
147
148 IsSyscall, ///< Causes a system call to be emulated in syscall
149 /// emulation mode.
150
151 //Flags for microcode
152 IsMacroop, ///< Is a macroop containing microops
153 IsMicroop, ///< Is a microop
154 IsDelayedCommit, ///< This microop doesn't commit right away
155 IsLastMicroop, ///< This microop ends a microop sequence
156 IsFirstMicroop, ///< This microop begins a microop sequence
157 //This flag doesn't do anything yet
158 IsMicroBranch, ///< This microop branches within the microcode for a macroop
159 IsDspOp,
160
161 NumFlags
162 };
163
164 /// Flag values for this instruction.
165 std::bitset<NumFlags> flags;
166
167 /// See opClass().
168 OpClass _opClass;
169
170 /// See numSrcRegs().
171 int8_t _numSrcRegs;
172
173 /// See numDestRegs().
174 int8_t _numDestRegs;
175
176 /// The following are used to track physical register usage
177 /// for machines with separate int & FP reg files.
178 //@{
179 int8_t _numFPDestRegs;
180 int8_t _numIntDestRegs;
181 //@}
182
183 /// Constructor.
184 /// It's important to initialize everything here to a sane
185 /// default, since the decoder generally only overrides
186 /// the fields that are meaningful for the particular
187 /// instruction.
188 StaticInstBase(OpClass __opClass)
189 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
190 _numFPDestRegs(0), _numIntDestRegs(0)
191 {
192 }
193
194 public:
195
196 /// @name Register information.
197 /// The sum of numFPDestRegs() and numIntDestRegs() equals
198 /// numDestRegs(). The former two functions are used to track
199 /// physical register usage for machines with separate int & FP
200 /// reg files.
201 //@{
202 /// Number of source registers.
203 int8_t numSrcRegs() const { return _numSrcRegs; }
204 /// Number of destination registers.
205 int8_t numDestRegs() const { return _numDestRegs; }
206 /// Number of floating-point destination regs.
207 int8_t numFPDestRegs() const { return _numFPDestRegs; }
208 /// Number of integer destination regs.
209 int8_t numIntDestRegs() const { return _numIntDestRegs; }
210 //@}
211
212 /// @name Flag accessors.
213 /// These functions are used to access the values of the various
214 /// instruction property flags. See StaticInstBase::Flags for descriptions
215 /// of the individual flags.
216 //@{
217
218 bool isNop() const { return flags[IsNop]; }
219
220 bool isMemRef() const { return flags[IsMemRef]; }
221 bool isLoad() const { return flags[IsLoad]; }
222 bool isStore() const { return flags[IsStore]; }
223 bool isStoreConditional() const { return flags[IsStoreConditional]; }
224 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
225 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
226 bool isCopy() const { return flags[IsCopy];}
227
228 bool isInteger() const { return flags[IsInteger]; }
229 bool isFloating() const { return flags[IsFloating]; }
230
231 bool isControl() const { return flags[IsControl]; }
232 bool isCall() const { return flags[IsCall]; }
233 bool isReturn() const { return flags[IsReturn]; }
234 bool isDirectCtrl() const { return flags[IsDirectControl]; }
235 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
236 bool isCondCtrl() const { return flags[IsCondControl]; }
237 bool isUncondCtrl() const { return flags[IsUncondControl]; }
238 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
239
240 bool isThreadSync() const { return flags[IsThreadSync]; }
241 bool isSerializing() const { return flags[IsSerializing] ||
242 flags[IsSerializeBefore] ||
243 flags[IsSerializeAfter]; }
244 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
245 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
246 bool isMemBarrier() const { return flags[IsMemBarrier]; }
247 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
248 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
249 bool isQuiesce() const { return flags[IsQuiesce]; }
250 bool isIprAccess() const { return flags[IsIprAccess]; }
251 bool isUnverifiable() const { return flags[IsUnverifiable]; }
252 bool isSyscall() const { return flags[IsSyscall]; }
253 bool isMacroop() const { return flags[IsMacroop]; }
254 bool isMicroop() const { return flags[IsMicroop]; }
255 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
256 bool isLastMicroop() const { return flags[IsLastMicroop]; }
257 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
258 //This flag doesn't do anything yet
259 bool isMicroBranch() const { return flags[IsMicroBranch]; }
260 //@}
261
262 void setLastMicroop() { flags[IsLastMicroop] = true; }
263 /// Operation class. Used to select appropriate function unit in issue.
264 OpClass opClass() const { return _opClass; }
265};
266
267
268// forward declaration
269class StaticInstPtr;
270
271/**
272 * Generic yet ISA-dependent static instruction class.
273 *
274 * This class builds on StaticInstBase, defining fields and interfaces
275 * that are generic across all ISAs but that differ in details
276 * according to the specific ISA being used.
277 */
278class StaticInst : public StaticInstBase
279{
280 public:
281
282 /// Binary machine instruction type.
283 typedef TheISA::MachInst MachInst;
284 /// Binary extended machine instruction type.
285 typedef TheISA::ExtMachInst ExtMachInst;
286 /// Logical register index type.
287 typedef TheISA::RegIndex RegIndex;
288
289 enum {
290 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
291 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
292 };
293
294
295 /// Return logical index (architectural reg num) of i'th destination reg.
296 /// Only the entries from 0 through numDestRegs()-1 are valid.
297 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
298
299 /// Return logical index (architectural reg num) of i'th source reg.
300 /// Only the entries from 0 through numSrcRegs()-1 are valid.
301 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
302
303 /// Pointer to a statically allocated "null" instruction object.
304 /// Used to give eaCompInst() and memAccInst() something to return
305 /// when called on non-memory instructions.
306 static StaticInstPtr nullStaticInstPtr;
307
308 /**
309 * Memory references only: returns "fake" instruction representing
310 * the effective address part of the memory operation. Used to
311 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
312 * just the EA computation.
313 */
314 virtual const
315 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
316
317 /**
318 * Memory references only: returns "fake" instruction representing
319 * the memory access part of the memory operation. Used to
320 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
321 * just the memory access (not the EA computation).
322 */
323 virtual const
324 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
325
326 /// The binary machine instruction.
327 const ExtMachInst machInst;
328
329 protected:
330
331 /// See destRegIdx().
332 RegIndex _destRegIdx[MaxInstDestRegs];
333 /// See srcRegIdx().
334 RegIndex _srcRegIdx[MaxInstSrcRegs];
335
336 /**
337 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
338 * methods. Also useful to readily identify instructions from
339 * within the debugger when #cachedDisassembly has not been
340 * initialized.
341 */
342 const char *mnemonic;
343
344 /**
345 * String representation of disassembly (lazily evaluated via
346 * disassemble()).
347 */
348 mutable std::string *cachedDisassembly;
349
350 /**
351 * Internal function to generate disassembly string.
352 */
353 virtual std::string
354 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
355
356 /// Constructor.
357 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
358 : StaticInstBase(__opClass),
359 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
360 { }
361
362 public:
363
364 virtual ~StaticInst()
365 {
366 if (cachedDisassembly)
367 delete cachedDisassembly;
368 }
369
370/**
371 * The execute() signatures are auto-generated by scons based on the
372 * set of CPU models we are compiling in today.
373 */
374#include "cpu/static_inst_exec_sigs.hh"
375
376 /**
377 * Return the microop that goes with a particular micropc. This should
378 * only be defined/used in macroops which will contain microops
379 */
380 virtual StaticInstPtr fetchMicroop(MicroPC micropc);
381
382 /**
383 * Return the target address for a PC-relative branch.
384 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
385 * should be true).
386 */
387 virtual Addr branchTarget(Addr branchPC) const
388 {
389 panic("StaticInst::branchTarget() called on instruction "
390 "that is not a PC-relative branch.");
391 M5_DUMMY_RETURN
392 }
393
394 /**
395 * Return the target address for an indirect branch (jump). The
396 * register value is read from the supplied thread context, so
397 * the result is valid only if the thread context is about to
398 * execute the branch in question. Invalid if not an indirect
399 * branch (i.e. isIndirectCtrl() should be true).
400 */
401 virtual Addr branchTarget(ThreadContext *tc) const
402 {
403 panic("StaticInst::branchTarget() called on instruction "
404 "that is not an indirect branch.");
405 M5_DUMMY_RETURN
406 }
407
408 /**
409 * Return true if the instruction is a control transfer, and if so,
410 * return the target address as well.
411 */
412 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
413
414 /**
415 * Return string representation of disassembled instruction.
416 * The default version of this function will call the internal
417 * virtual generateDisassembly() function to get the string,
418 * then cache it in #cachedDisassembly. If the disassembly
419 * should not be cached, this function should be overridden directly.
420 */
421 virtual const std::string &disassemble(Addr pc,
422 const SymbolTable *symtab = 0) const
423 {
424 if (!cachedDisassembly)
425 cachedDisassembly =
426 new std::string(generateDisassembly(pc, symtab));
427
428 return *cachedDisassembly;
429 }
430
431 /// Decoded instruction cache type.
432 /// For now we're using a generic hash_map; this seems to work
433 /// pretty well.
434 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
435
436 /// A cache of decoded instruction objects.
437 static DecodeCache decodeCache;
438
439 /**
440 * Dump some basic stats on the decode cache hash map.
441 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
442 */
443 static void dumpDecodeCacheStats();
444
445 /// Decode a machine instruction.
446 /// @param mach_inst The binary instruction to decode.
447 /// @retval A pointer to the corresponding StaticInst object.
448 //This is defined as inlined below.
449 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
450
451 /// Return name of machine instruction
452 std::string getName() { return mnemonic; }
453
454 /// Decoded instruction cache type, for address decoding.
455 /// A generic hash_map is used.
456 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
457
458 /// A cache of decoded instruction objects from addresses.
459 static AddrDecodeCache addrDecodeCache;
460
461 struct cacheElement {
462 Addr page_addr;
463 AddrDecodePage *decodePage;
464
465 cacheElement()
466 :decodePage(NULL) { }
467 } ;
468
469 /// An array of recently decoded instructions.
470 // might not use an array if there is only two elements
471 static struct cacheElement recentDecodes[2];
472
473 /// Updates the recently decoded instructions entries
474 /// @param page_addr The page address recently used.
475 /// @param decodePage Pointer to decoding page containing the decoded
476 /// instruction.
477 static inline void
478 updateCache(Addr page_addr, AddrDecodePage *decodePage)
479 {
480 recentDecodes[1].page_addr = recentDecodes[0].page_addr;
481 recentDecodes[1].decodePage = recentDecodes[0].decodePage;
482 recentDecodes[0].page_addr = page_addr;
483 recentDecodes[0].decodePage = decodePage;
484 }
485
486 /// Searches the decoded instruction cache for instruction decoding.
487 /// If it is not found, then we decode the instruction.
488 /// Otherwise, we get the instruction from the cache and move it into
489 /// the address-to-instruction decoding page.
490 /// @param mach_inst The binary instruction to decode.
491 /// @param addr The address that contained the binary instruction.
492 /// @param decodePage Pointer to decoding page containing the instruction.
493 /// @retval A pointer to the corresponding StaticInst object.
494 //This is defined as inlined below.
495 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
496 AddrDecodePage * decodePage);
497};
498
499typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
500
501/// Reference-counted pointer to a StaticInst object.
502/// This type should be used instead of "StaticInst *" so that
503/// StaticInst objects can be properly reference-counted.
504class StaticInstPtr : public RefCountingPtr<StaticInst>
505{
506 public:
507 /// Constructor.
508 StaticInstPtr()
509 : RefCountingPtr<StaticInst>()
510 {
511 }
512
513 /// Conversion from "StaticInst *".
514 StaticInstPtr(StaticInst *p)
515 : RefCountingPtr<StaticInst>(p)
516 {
517 }
518
519 /// Copy constructor.
520 StaticInstPtr(const StaticInstPtr &r)
521 : RefCountingPtr<StaticInst>(r)
522 {
523 }
524
525 /// Construct directly from machine instruction.
526 /// Calls StaticInst::decode().
527 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
528 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
529 {
530 }
531
532 /// Convert to pointer to StaticInstBase class.
533 operator const StaticInstBasePtr()
534 {
535 return this->get();
536 }
537};
538
539/// A page of a list of decoded instructions from an address.
540class AddrDecodePage
541{
542 typedef TheISA::ExtMachInst ExtMachInst;
543 protected:
544 StaticInstPtr instructions[TheISA::PageBytes];
545 bool valid[TheISA::PageBytes];
546 Addr lowerMask;
547
548 public:
549 /// Constructor
550 AddrDecodePage() {
551 lowerMask = TheISA::PageBytes - 1;
552 memset(valid, 0, TheISA::PageBytes);
553 }
554
555 /// Checks if the instruction is already decoded and the machine
556 /// instruction in the cache matches the current machine instruction
557 /// related to the address
558 /// @param mach_inst The binary instruction to check
559 /// @param addr The address containing the instruction
560 inline bool decoded(ExtMachInst mach_inst, Addr addr)
561 {
562 return (valid[addr & lowerMask] &&
563 (instructions[addr & lowerMask]->machInst == mach_inst));
564 }
565
566 /// Returns the instruction object. decoded should be called first
567 /// to check if the instruction is valid.
568 /// @param addr The address of the instruction.
569 /// @retval A pointer to the corresponding StaticInst object.
570 inline StaticInstPtr getInst(Addr addr)
571 { return instructions[addr & lowerMask]; }
572
573 /// Inserts a pointer to a StaticInst object into the list of decoded
574 /// instructions on the page.
575 /// @param addr The address of the instruction.
576 /// @param si A pointer to the corresponding StaticInst object.
577 inline void insert(Addr addr, StaticInstPtr &si)
578 {
579 instructions[addr & lowerMask] = si;
580 valid[addr & lowerMask] = true;
581 }
582
583};
584
585
586inline StaticInstPtr
587StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
588{
589#ifdef DECODE_CACHE_HASH_STATS
590 // Simple stats on decode hash_map. Turns out the default
591 // hash function is as good as anything I could come up with.
592 const int dump_every_n = 10000000;
593 static int decodes_til_dump = dump_every_n;
594
595 if (--decodes_til_dump == 0) {
596 dumpDecodeCacheStats();
597 decodes_til_dump = dump_every_n;
598 }
599#endif
600
601 Addr page_addr = addr & ~(TheISA::PageBytes - 1);
602
603 // checks recently decoded addresses
604 if (recentDecodes[0].decodePage &&
605 page_addr == recentDecodes[0].page_addr) {
606 if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
607 return recentDecodes[0].decodePage->getInst(addr);
608
609 return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
610 }
611
612 if (recentDecodes[1].decodePage &&
613 page_addr == recentDecodes[1].page_addr) {
614 if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
615 return recentDecodes[1].decodePage->getInst(addr);
616
617 return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
618 }
619
620 // searches the page containing the address to decode
621 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
622 if (iter != addrDecodeCache.end()) {
623 updateCache(page_addr, iter->second);
624 if (iter->second->decoded(mach_inst, addr))
625 return iter->second->getInst(addr);
626
627 return searchCache(mach_inst, addr, iter->second);
628 }
629
630 // creates a new object for a page of decoded instructions
631 AddrDecodePage * decodePage = new AddrDecodePage;
632 addrDecodeCache[page_addr] = decodePage;
633 updateCache(page_addr, decodePage);
634 return searchCache(mach_inst, addr, decodePage);
635}
636
637inline StaticInstPtr
638StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
639 AddrDecodePage * decodePage)
640{
641 DecodeCache::iterator iter = decodeCache.find(mach_inst);
642 if (iter != decodeCache.end()) {
643 decodePage->insert(addr, iter->second);
644 return iter->second;
645 }
646
647 StaticInstPtr si = TheISA::decodeInst(mach_inst);
648 decodePage->insert(addr, si);
649 decodeCache[mach_inst] = si;
650 return si;
651}
652
653#endif // __CPU_STATIC_INST_HH__