1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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374 * Return the target address for a PC-relative branch.
375 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
376 * should be true).
377 */
378 virtual Addr branchTarget(Addr branchPC) const
379 {
380 panic("StaticInst::branchTarget() called on instruction "
381 "that is not a PC-relative branch.");
382 M5_DUMMY_RETURN
383 }
384
385 /**
386 * Return the target address for an indirect branch (jump). The
387 * register value is read from the supplied thread context, so
388 * the result is valid only if the thread context is about to
389 * execute the branch in question. Invalid if not an indirect
390 * branch (i.e. isIndirectCtrl() should be true).
391 */
392 virtual Addr branchTarget(ThreadContext *tc) const
393 {
394 panic("StaticInst::branchTarget() called on instruction "
395 "that is not an indirect branch.");
396 }
397 M5_DUMMY_RETURN
398
399 /**
400 * Return true if the instruction is a control transfer, and if so,
401 * return the target address as well.
402 */
403 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
404
405 /**

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