1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "base/hashmap.hh"
38#include "base/misc.hh"
39#include "base/refcnt.hh"
40#include "cpu/op_class.hh"
41#include "sim/host.hh"
42#include "arch/isa_traits.hh"
43
44// forward declarations
45struct AlphaSimpleImpl;
46class ExecContext;
47class DynInst;
48class Packet;
49
50template <class Impl>
51class AlphaDynInst;
52
53class FastCPU;
54class AtomicSimpleCPU;
55class TimingSimpleCPU;
56class InorderCPU;
57class SymbolTable;
58
59namespace Trace {
60 class InstRecord;

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97 IsNop, ///< Is a no-op (no effect at all).
98
99 IsInteger, ///< References integer regs.
100 IsFloating, ///< References FP regs.
101
102 IsMemRef, ///< References memory (load, store, or prefetch).
103 IsLoad, ///< Reads from memory (load or prefetch).
104 IsStore, ///< Writes to memory.
105 IsInstPrefetch, ///< Instruction-cache prefetch.
106 IsDataPrefetch, ///< Data-cache prefetch.
107 IsCopy, ///< Fast Cache block copy
108
109 IsControl, ///< Control transfer instruction.
110 IsDirectControl, ///< PC relative control transfer.
111 IsIndirectControl, ///< Register indirect control transfer.
112 IsCondControl, ///< Conditional control transfer.

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121 IsSerializing, ///< Serializes pipeline: won't execute until all
122 /// older instructions have committed.
123 IsSerializeBefore,
124 IsSerializeAfter,
125 IsMemBarrier, ///< Is a memory barrier
126 IsWriteBarrier, ///< Is a write barrier
127
128 IsNonSpeculative, ///< Should not be executed speculatively
129
130 NumFlags
131 };
132
133 /// Flag values for this instruction.
134 std::bitset<NumFlags> flags;
135
136 /// See opClass().
137 OpClass _opClass;

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184 /// of the individual flags.
185 //@{
186
187 bool isNop() const { return flags[IsNop]; }
188
189 bool isMemRef() const { return flags[IsMemRef]; }
190 bool isLoad() const { return flags[IsLoad]; }
191 bool isStore() const { return flags[IsStore]; }
192 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
193 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
194 bool isCopy() const { return flags[IsCopy];}
195
196 bool isInteger() const { return flags[IsInteger]; }
197 bool isFloating() const { return flags[IsFloating]; }
198
199 bool isControl() const { return flags[IsControl]; }

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208 bool isSerializing() const { return flags[IsSerializing] ||
209 flags[IsSerializeBefore] ||
210 flags[IsSerializeAfter]; }
211 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
212 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
213 bool isMemBarrier() const { return flags[IsMemBarrier]; }
214 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
215 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
216 //@}
217
218 /// Operation class. Used to select appropriate function unit in issue.
219 OpClass opClass() const { return _opClass; }
220};
221
222
223// forward declaration

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