static_inst.cc (6192:6cd5f0282d8a) | static_inst.cc (7720:65d338a8dba4) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 54 unchanged lines hidden (view full) --- 63 hist[count]++; 64 } 65 for (int i = 0; i <= max_hist; ++i) { 66 cerr << "\tbuckets of size " << i << " = " << hist[i] << endl; 67 } 68} 69 70bool | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 54 unchanged lines hidden (view full) --- 63 hist[count]++; 64 } 65 for (int i = 0; i <= max_hist; ++i) { 66 cerr << "\tbuckets of size " << i << " = " << hist[i] << endl; 67 } 68} 69 70bool |
71StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const | 71StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 72 TheISA::PCState &tgt) const |
72{ 73 if (isDirectCtrl()) { 74 tgt = branchTarget(pc); 75 return true; 76 } 77 78 if (isIndirectCtrl()) { 79 tgt = branchTarget(tc); 80 return true; 81 } 82 83 return false; 84} 85 86StaticInstPtr | 73{ 74 if (isDirectCtrl()) { 75 tgt = branchTarget(pc); 76 return true; 77 } 78 79 if (isIndirectCtrl()) { 80 tgt = branchTarget(tc); 81 return true; 82 } 83 84 return false; 85} 86 87StaticInstPtr |
87StaticInst::fetchMicroop(MicroPC micropc) | 88StaticInst::fetchMicroop(MicroPC upc) const |
88{ 89 panic("StaticInst::fetchMicroop() called on instruction " 90 "that is not microcoded."); 91} 92 | 89{ 90 panic("StaticInst::fetchMicroop() called on instruction " 91 "that is not microcoded."); 92} 93 |
93Addr 94StaticInst::branchTarget(Addr branchPC) const | 94TheISA::PCState 95StaticInst::branchTarget(const TheISA::PCState &pc) const |
95{ 96 panic("StaticInst::branchTarget() called on instruction " 97 "that is not a PC-relative branch."); 98 M5_DUMMY_RETURN; 99} 100 | 96{ 97 panic("StaticInst::branchTarget() called on instruction " 98 "that is not a PC-relative branch."); 99 M5_DUMMY_RETURN; 100} 101 |
101Addr | 102TheISA::PCState |
102StaticInst::branchTarget(ThreadContext *tc) const 103{ 104 panic("StaticInst::branchTarget() called on instruction " 105 "that is not an indirect branch."); 106 M5_DUMMY_RETURN; 107} 108 109const string & 110StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const 111{ 112 if (!cachedDisassembly) 113 cachedDisassembly = new string(generateDisassembly(pc, symtab)); 114 115 return *cachedDisassembly; 116} | 103StaticInst::branchTarget(ThreadContext *tc) const 104{ 105 panic("StaticInst::branchTarget() called on instruction " 106 "that is not an indirect branch."); 107 M5_DUMMY_RETURN; 108} 109 110const string & 111StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const 112{ 113 if (!cachedDisassembly) 114 cachedDisassembly = new string(generateDisassembly(pc, symtab)); 115 116 return *cachedDisassembly; 117} |