1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#include "cpu/static_inst.hh"
33
34#include <iostream>
35
36#include "sim/core.hh"
37
38namespace {
39
40static TheISA::ExtMachInst nopMachInst;
41
42class NopStaticInst : public StaticInst
43{
44 public:
45 NopStaticInst() : StaticInst("gem5 nop", nopMachInst, No_OpClass)
46 {}
47
48 Fault
49 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
50 {
51 return NoFault;
52 }
53
54 void
55 advancePC(TheISA::PCState &pcState) const override
56 {
57 pcState.advance();
58 }
59
60 std::string
61 generateDisassembly(Addr pc, const SymbolTable *symtab) const override
62 {
63 return mnemonic;
64 }
65
66 private:
67};
68
69}
70
71StaticInstPtr StaticInst::nullStaticInstPtr;
72StaticInstPtr StaticInst::nopStaticInstPtr = new NopStaticInst;
73
74using namespace std;
75
76StaticInst::~StaticInst()
77{
78 if (cachedDisassembly)
79 delete cachedDisassembly;
80}
81
82bool
83StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
84 TheISA::PCState &tgt) const
85{
86 if (isDirectCtrl()) {
87 tgt = branchTarget(pc);
88 return true;
89 }
90
91 if (isIndirectCtrl()) {
92 tgt = branchTarget(tc);
93 return true;
94 }
95
96 return false;
97}
98
99StaticInstPtr
100StaticInst::fetchMicroop(MicroPC upc) const
101{
102 panic("StaticInst::fetchMicroop() called on instruction "
103 "that is not microcoded.");
104}
105
106TheISA::PCState
107StaticInst::branchTarget(const TheISA::PCState &pc) const
108{
109 panic("StaticInst::branchTarget() called on instruction "
110 "that is not a PC-relative branch.");
111 M5_DUMMY_RETURN;
112}
113
114TheISA::PCState
115StaticInst::branchTarget(ThreadContext *tc) const
116{
117 panic("StaticInst::branchTarget() called on instruction "
118 "that is not an indirect branch.");
119 M5_DUMMY_RETURN;
120}
121
122const string &
123StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
124{
125 if (!cachedDisassembly)
126 cachedDisassembly = new string(generateDisassembly(pc, symtab));
127
128 return *cachedDisassembly;
129}
130
131void
132StaticInst::printFlags(std::ostream &outs,
133 const std::string &separator) const
134{
135 bool printed_a_flag = false;
136
137 for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
138 if (flags[flag]) {
139 if (printed_a_flag)
140 outs << separator;
141
142 outs << FlagsStrings[flag];
143 printed_a_flag = true;
144 }
145 }
146}