1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
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36#include "sim/core.hh"
37
38StaticInstPtr StaticInst::nullStaticInstPtr;
39
40using namespace std;
41
42StaticInst::~StaticInst()
43{
44 if (cachedDisassembly)
45 delete cachedDisassembly;
46}
47
48bool
49StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
50 TheISA::PCState &tgt) const
51{
52 if (isDirectCtrl()) {
53 tgt = branchTarget(pc);
54 return true;
55 }
56
57 if (isIndirectCtrl()) {
58 tgt = branchTarget(tc);
59 return true;
60 }
61
62 return false;
63}
64
65StaticInstPtr
66StaticInst::fetchMicroop(MicroPC upc) const
67{
68 panic("StaticInst::fetchMicroop() called on instruction "
69 "that is not microcoded.");
70}
71
72TheISA::PCState
73StaticInst::branchTarget(const TheISA::PCState &pc) const
74{
75 panic("StaticInst::branchTarget() called on instruction "
76 "that is not a PC-relative branch.");
77 M5_DUMMY_RETURN;
78}
79
80TheISA::PCState
81StaticInst::branchTarget(ThreadContext *tc) const
82{
83 panic("StaticInst::branchTarget() called on instruction "
84 "that is not an indirect branch.");
85 M5_DUMMY_RETURN;
86}
87
88const string &
89StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
90{
91 if (!cachedDisassembly)
92 cachedDisassembly = new string(generateDisassembly(pc, symtab));
93
94 return *cachedDisassembly;
95}
96
97void
98StaticInst::printFlags(std::ostream &outs,
99 const std::string &separator) const
100{
101 bool printed_a_flag = false;
102
103 for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
104 if (flags[flag]) {
105 if (printed_a_flag)
106 outs << separator;
107
108 outs << FlagsStrings[flag];
109 printed_a_flag = true;
110 }
111 }
112}
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