1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31 32#include <iostream> 33 34#include "cpu/static_inst.hh" 35#include "sim/core.hh" 36 37StaticInstPtr StaticInst::nullStaticInstPtr; 38 |
39using namespace std; 40 41StaticInst::~StaticInst() 42{ 43 if (cachedDisassembly) 44 delete cachedDisassembly; 45} 46 |
47bool 48StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 49 TheISA::PCState &tgt) const 50{ 51 if (isDirectCtrl()) { 52 tgt = branchTarget(pc); 53 return true; 54 } --- 40 unchanged lines hidden --- |