1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#include "cpu/static_inst.hh" 33 34#include <iostream> 35 36#include "sim/core.hh" 37 |
38namespace { 39 40static TheISA::ExtMachInst nopMachInst; 41 42class NopStaticInst : public StaticInst 43{ 44 public: 45 NopStaticInst() : StaticInst("gem5 nop", nopMachInst, No_OpClass) 46 {} 47 48 Fault 49 execute(ExecContext *xc, Trace::InstRecord *traceData) const override 50 { 51 return NoFault; 52 } 53 54 void 55 advancePC(TheISA::PCState &pcState) const override 56 { 57 pcState.advance(); 58 } 59 60 std::string 61 generateDisassembly(Addr pc, const SymbolTable *symtab) const override 62 { 63 return mnemonic; 64 } 65 66 private: 67}; 68 69} 70 |
71StaticInstPtr StaticInst::nullStaticInstPtr; |
72StaticInstPtr StaticInst::nopStaticInstPtr = new NopStaticInst; |
73 74using namespace std; 75 76StaticInst::~StaticInst() 77{ 78 if (cachedDisassembly) 79 delete cachedDisassembly; 80} --- 66 unchanged lines hidden --- |