simple_thread.hh (9461:67a6ba6604c8) simple_thread.hh (9920:028e4da64b42)
1/*
2 * Copyright (c) 2011 ARM Limited
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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49#include "arch/isa_traits.hh"
50#include "arch/registers.hh"
51#include "arch/tlb.hh"
52#include "arch/types.hh"
53#include "base/types.hh"
54#include "config/the_isa.hh"
55#include "cpu/thread_context.hh"
56#include "cpu/thread_state.hh"
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "arch/tlb.hh"
53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
57#include "debug/FloatRegs.hh"
58#include "debug/IntRegs.hh"
59#include "mem/page_table.hh"
60#include "mem/request.hh"
61#include "sim/byteswap.hh"
62#include "sim/eventq.hh"
63#include "sim/process.hh"
64#include "sim/serialize.hh"

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94
95class SimpleThread : public ThreadState
96{
97 protected:
98 typedef TheISA::MachInst MachInst;
99 typedef TheISA::MiscReg MiscReg;
100 typedef TheISA::FloatReg FloatReg;
101 typedef TheISA::FloatRegBits FloatRegBits;
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
61#include "mem/page_table.hh"
62#include "mem/request.hh"
63#include "sim/byteswap.hh"
64#include "sim/eventq.hh"
65#include "sim/process.hh"
66#include "sim/serialize.hh"

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96
97class SimpleThread : public ThreadState
98{
99 protected:
100 typedef TheISA::MachInst MachInst;
101 typedef TheISA::MiscReg MiscReg;
102 typedef TheISA::FloatReg FloatReg;
103 typedef TheISA::FloatRegBits FloatRegBits;
104 typedef TheISA::CCReg CCReg;
102 public:
103 typedef ThreadContext::Status Status;
104
105 protected:
106 union {
107 FloatReg f[TheISA::NumFloatRegs];
108 FloatRegBits i[TheISA::NumFloatRegs];
109 } floatRegs;
110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
105 public:
106 typedef ThreadContext::Status Status;
107
108 protected:
109 union {
110 FloatReg f[TheISA::NumFloatRegs];
111 FloatRegBits i[TheISA::NumFloatRegs];
112 } floatRegs;
113 TheISA::IntReg intRegs[TheISA::NumIntRegs];
114#ifdef ISA_HAS_CC_REGS
115 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
116#endif
111 TheISA::ISA *const isa; // one "instance" of the current ISA.
112
113 TheISA::PCState _pcState;
114
115 /** Did this instruction execute or is it predicated false */
116 bool predicate;
117
118 public:

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219
220 void copyArchRegs(ThreadContext *tc);
221
222 void clearArchRegs()
223 {
224 _pcState = 0;
225 memset(intRegs, 0, sizeof(intRegs));
226 memset(floatRegs.i, 0, sizeof(floatRegs.i));
117 TheISA::ISA *const isa; // one "instance" of the current ISA.
118
119 TheISA::PCState _pcState;
120
121 /** Did this instruction execute or is it predicated false */
122 bool predicate;
123
124 public:

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225
226 void copyArchRegs(ThreadContext *tc);
227
228 void clearArchRegs()
229 {
230 _pcState = 0;
231 memset(intRegs, 0, sizeof(intRegs));
232 memset(floatRegs.i, 0, sizeof(floatRegs.i));
233#ifdef ISA_HAS_CC_REGS
234 memset(ccRegs, 0, sizeof(ccRegs));
235#endif
227 isa->clear();
228 }
229
230 //
231 // New accessors for new decoder.
232 //
233 uint64_t readIntReg(int reg_idx)
234 {

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255 int flatIndex = isa->flattenFloatIndex(reg_idx);
256 assert(flatIndex < TheISA::NumFloatRegs);
257 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
258 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
259 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
260 return regVal;
261 }
262
236 isa->clear();
237 }
238
239 //
240 // New accessors for new decoder.
241 //
242 uint64_t readIntReg(int reg_idx)
243 {

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264 int flatIndex = isa->flattenFloatIndex(reg_idx);
265 assert(flatIndex < TheISA::NumFloatRegs);
266 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
267 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
268 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
269 return regVal;
270 }
271
272 CCReg readCCReg(int reg_idx)
273 {
274#ifdef ISA_HAS_CC_REGS
275 int flatIndex = isa->flattenCCIndex(reg_idx);
276 assert(flatIndex < TheISA::NumCCRegs);
277 uint64_t regVal(readCCRegFlat(flatIndex));
278 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
279 reg_idx, flatIndex, regVal);
280 return regVal;
281#else
282 panic("Tried to read a CC register.");
283 return 0;
284#endif
285 }
286
263 void setIntReg(int reg_idx, uint64_t val)
264 {
265 int flatIndex = isa->flattenIntIndex(reg_idx);
266 assert(flatIndex < TheISA::NumIntRegs);
267 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
268 reg_idx, flatIndex, val);
269 setIntRegFlat(flatIndex, val);
270 }

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285 // XXX: Fix array out of bounds compiler error for gem5.fast
286 // when checkercpu enabled
287 if (flatIndex < TheISA::NumFloatRegs)
288 setFloatRegBitsFlat(flatIndex, val);
289 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
290 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
291 }
292
287 void setIntReg(int reg_idx, uint64_t val)
288 {
289 int flatIndex = isa->flattenIntIndex(reg_idx);
290 assert(flatIndex < TheISA::NumIntRegs);
291 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
292 reg_idx, flatIndex, val);
293 setIntRegFlat(flatIndex, val);
294 }

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309 // XXX: Fix array out of bounds compiler error for gem5.fast
310 // when checkercpu enabled
311 if (flatIndex < TheISA::NumFloatRegs)
312 setFloatRegBitsFlat(flatIndex, val);
313 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
314 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
315 }
316
317 void setCCReg(int reg_idx, CCReg val)
318 {
319#ifdef ISA_HAS_CC_REGS
320 int flatIndex = isa->flattenCCIndex(reg_idx);
321 assert(flatIndex < TheISA::NumCCRegs);
322 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
323 reg_idx, flatIndex, val);
324 setCCRegFlat(flatIndex, val);
325#else
326 panic("Tried to set a CC register.");
327#endif
328 }
329
293 TheISA::PCState
294 pcState()
295 {
296 return _pcState;
297 }
298
299 void
300 pcState(const TheISA::PCState &val)

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367 }
368
369 int
370 flattenFloatIndex(int reg)
371 {
372 return isa->flattenFloatIndex(reg);
373 }
374
330 TheISA::PCState
331 pcState()
332 {
333 return _pcState;
334 }
335
336 void
337 pcState(const TheISA::PCState &val)

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404 }
405
406 int
407 flattenFloatIndex(int reg)
408 {
409 return isa->flattenFloatIndex(reg);
410 }
411
412 int
413 flattenCCIndex(int reg)
414 {
415 return isa->flattenCCIndex(reg);
416 }
417
375 unsigned readStCondFailures() { return storeCondFailures; }
376
377 void setStCondFailures(unsigned sc_failures)
378 { storeCondFailures = sc_failures; }
379
380 void syscall(int64_t callnum)
381 {
382 process->syscall(callnum, tc);

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388 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
389 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
390
391 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
392 void setFloatRegBitsFlat(int idx, FloatRegBits val) {
393 floatRegs.i[idx] = val;
394 }
395
418 unsigned readStCondFailures() { return storeCondFailures; }
419
420 void setStCondFailures(unsigned sc_failures)
421 { storeCondFailures = sc_failures; }
422
423 void syscall(int64_t callnum)
424 {
425 process->syscall(callnum, tc);

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431 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
432 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
433
434 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
435 void setFloatRegBitsFlat(int idx, FloatRegBits val) {
436 floatRegs.i[idx] = val;
437 }
438
439#ifdef ISA_HAS_CC_REGS
440 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
441 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
442#else
443 CCReg readCCRegFlat(int idx)
444 { panic("readCCRegFlat w/no CC regs!\n"); }
445
446 void setCCRegFlat(int idx, CCReg val)
447 { panic("setCCRegFlat w/no CC regs!\n"); }
448#endif
396};
397
398
399// for non-speculative execution context, spec_mode is always false
400inline bool
401SimpleThread::misspeculating()
402{
403 return false;
404}
405
406#endif // __CPU_CPU_EXEC_CONTEXT_HH__
449};
450
451
452// for non-speculative execution context, spec_mode is always false
453inline bool
454SimpleThread::misspeculating()
455{
456 return false;
457}
458
459#endif // __CPU_CPU_EXEC_CONTEXT_HH__