simple_thread.hh (9384:877293183bdf) | simple_thread.hh (9426:0548b3e9734d) |
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1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 223 unchanged lines hidden (view full) --- 232 233 // 234 // New accessors for new decoder. 235 // 236 uint64_t readIntReg(int reg_idx) 237 { 238 int flatIndex = isa->flattenIntIndex(reg_idx); 239 assert(flatIndex < TheISA::NumIntRegs); | 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 223 unchanged lines hidden (view full) --- 232 233 // 234 // New accessors for new decoder. 235 // 236 uint64_t readIntReg(int reg_idx) 237 { 238 int flatIndex = isa->flattenIntIndex(reg_idx); 239 assert(flatIndex < TheISA::NumIntRegs); |
240 uint64_t regVal = intRegs[flatIndex]; | 240 uint64_t regVal(readIntRegFlat(flatIndex)); |
241 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 242 reg_idx, flatIndex, regVal); 243 return regVal; 244 } 245 246 FloatReg readFloatReg(int reg_idx) 247 { 248 int flatIndex = isa->flattenFloatIndex(reg_idx); 249 assert(flatIndex < TheISA::NumFloatRegs); | 241 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 242 reg_idx, flatIndex, regVal); 243 return regVal; 244 } 245 246 FloatReg readFloatReg(int reg_idx) 247 { 248 int flatIndex = isa->flattenFloatIndex(reg_idx); 249 assert(flatIndex < TheISA::NumFloatRegs); |
250 FloatReg regVal = floatRegs.f[flatIndex]; | 250 FloatReg regVal(readFloatRegFlat(flatIndex)); |
251 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 252 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 253 return regVal; 254 } 255 256 FloatRegBits readFloatRegBits(int reg_idx) 257 { 258 int flatIndex = isa->flattenFloatIndex(reg_idx); 259 assert(flatIndex < TheISA::NumFloatRegs); | 251 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 252 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 253 return regVal; 254 } 255 256 FloatRegBits readFloatRegBits(int reg_idx) 257 { 258 int flatIndex = isa->flattenFloatIndex(reg_idx); 259 assert(flatIndex < TheISA::NumFloatRegs); |
260 FloatRegBits regVal = floatRegs.i[flatIndex]; | 260 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); |
261 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 262 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 263 return regVal; 264 } 265 266 void setIntReg(int reg_idx, uint64_t val) 267 { 268 int flatIndex = isa->flattenIntIndex(reg_idx); 269 assert(flatIndex < TheISA::NumIntRegs); 270 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 271 reg_idx, flatIndex, val); | 261 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 262 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 263 return regVal; 264 } 265 266 void setIntReg(int reg_idx, uint64_t val) 267 { 268 int flatIndex = isa->flattenIntIndex(reg_idx); 269 assert(flatIndex < TheISA::NumIntRegs); 270 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 271 reg_idx, flatIndex, val); |
272 intRegs[flatIndex] = val; | 272 setIntRegFlat(flatIndex, val); |
273 } 274 275 void setFloatReg(int reg_idx, FloatReg val) 276 { 277 int flatIndex = isa->flattenFloatIndex(reg_idx); 278 assert(flatIndex < TheISA::NumFloatRegs); | 273 } 274 275 void setFloatReg(int reg_idx, FloatReg val) 276 { 277 int flatIndex = isa->flattenFloatIndex(reg_idx); 278 assert(flatIndex < TheISA::NumFloatRegs); |
279 floatRegs.f[flatIndex] = val; | 279 setFloatRegFlat(flatIndex, val); |
280 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 281 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 282 } 283 284 void setFloatRegBits(int reg_idx, FloatRegBits val) 285 { 286 int flatIndex = isa->flattenFloatIndex(reg_idx); 287 assert(flatIndex < TheISA::NumFloatRegs); 288 // XXX: Fix array out of bounds compiler error for gem5.fast 289 // when checkercpu enabled 290 if (flatIndex < TheISA::NumFloatRegs) | 280 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 281 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 282 } 283 284 void setFloatRegBits(int reg_idx, FloatRegBits val) 285 { 286 int flatIndex = isa->flattenFloatIndex(reg_idx); 287 assert(flatIndex < TheISA::NumFloatRegs); 288 // XXX: Fix array out of bounds compiler error for gem5.fast 289 // when checkercpu enabled 290 if (flatIndex < TheISA::NumFloatRegs) |
291 floatRegs.i[flatIndex] = val; | 291 setFloatRegBitsFlat(flatIndex, val); |
292 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 293 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 294 } 295 296 TheISA::PCState 297 pcState() 298 { 299 return _pcState; --- 79 unchanged lines hidden (view full) --- 379 380 void setStCondFailures(unsigned sc_failures) 381 { storeCondFailures = sc_failures; } 382 383 void syscall(int64_t callnum) 384 { 385 process->syscall(callnum, tc); 386 } | 292 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 293 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 294 } 295 296 TheISA::PCState 297 pcState() 298 { 299 return _pcState; --- 79 unchanged lines hidden (view full) --- 379 380 void setStCondFailures(unsigned sc_failures) 381 { storeCondFailures = sc_failures; } 382 383 void syscall(int64_t callnum) 384 { 385 process->syscall(callnum, tc); 386 } |
387 388 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 389 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 390 391 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 392 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 393 394 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 395 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 396 floatRegs.i[idx] = val; 397 } 398 |
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387}; 388 389 390// for non-speculative execution context, spec_mode is always false 391inline bool 392SimpleThread::misspeculating() 393{ 394 return false; 395} 396 397#endif // __CPU_CPU_EXEC_CONTEXT_HH__ | 399}; 400 401 402// for non-speculative execution context, spec_mode is always false 403inline bool 404SimpleThread::misspeculating() 405{ 406 return false; 407} 408 409#endif // __CPU_CPU_EXEC_CONTEXT_HH__ |