simple_thread.hh (9180:ee8d7a51651d) simple_thread.hh (9384:877293183bdf)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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103 typedef ThreadContext::Status Status;
104
105 protected:
106 union {
107 FloatReg f[TheISA::NumFloatRegs];
108 FloatRegBits i[TheISA::NumFloatRegs];
109 } floatRegs;
110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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103 typedef ThreadContext::Status Status;
104
105 protected:
106 union {
107 FloatReg f[TheISA::NumFloatRegs];
108 FloatRegBits i[TheISA::NumFloatRegs];
109 } floatRegs;
110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
111 TheISA::ISA isa; // one "instance" of the current ISA.
111 TheISA::ISA *const isa; // one "instance" of the current ISA.
112
113 TheISA::PCState _pcState;
114
115 /** Did this instruction execute or is it predicated false */
116 bool predicate;
117
118 public:
119 std::string name() const

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128 TheISA::TLB *itb;
129 TheISA::TLB *dtb;
130
131 TheISA::Decoder decoder;
132
133 // constructor: initialize SimpleThread from given process structure
134 // FS
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
112
113 TheISA::PCState _pcState;
114
115 /** Did this instruction execute or is it predicated false */
116 bool predicate;
117
118 public:
119 std::string name() const

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128 TheISA::TLB *itb;
129 TheISA::TLB *dtb;
130
131 TheISA::Decoder decoder;
132
133 // constructor: initialize SimpleThread from given process structure
134 // FS
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
137 bool use_kernel_stats = true);
138 // SE
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
137 bool use_kernel_stats = true);
138 // SE
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
141 TheISA::ISA *_isa);
141
142 SimpleThread();
143
144 virtual ~SimpleThread();
145
146 virtual void takeOverFrom(ThreadContext *oldContext);
147
148 void regStats(const std::string &name);

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221
222 void copyArchRegs(ThreadContext *tc);
223
224 void clearArchRegs()
225 {
226 _pcState = 0;
227 memset(intRegs, 0, sizeof(intRegs));
228 memset(floatRegs.i, 0, sizeof(floatRegs.i));
142
143 SimpleThread();
144
145 virtual ~SimpleThread();
146
147 virtual void takeOverFrom(ThreadContext *oldContext);
148
149 void regStats(const std::string &name);

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222
223 void copyArchRegs(ThreadContext *tc);
224
225 void clearArchRegs()
226 {
227 _pcState = 0;
228 memset(intRegs, 0, sizeof(intRegs));
229 memset(floatRegs.i, 0, sizeof(floatRegs.i));
229 isa.clear();
230 isa->clear();
230 }
231
232 //
233 // New accessors for new decoder.
234 //
235 uint64_t readIntReg(int reg_idx)
236 {
231 }
232
233 //
234 // New accessors for new decoder.
235 //
236 uint64_t readIntReg(int reg_idx)
237 {
237 int flatIndex = isa.flattenIntIndex(reg_idx);
238 int flatIndex = isa->flattenIntIndex(reg_idx);
238 assert(flatIndex < TheISA::NumIntRegs);
239 uint64_t regVal = intRegs[flatIndex];
240 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
241 reg_idx, flatIndex, regVal);
242 return regVal;
243 }
244
245 FloatReg readFloatReg(int reg_idx)
246 {
239 assert(flatIndex < TheISA::NumIntRegs);
240 uint64_t regVal = intRegs[flatIndex];
241 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
242 reg_idx, flatIndex, regVal);
243 return regVal;
244 }
245
246 FloatReg readFloatReg(int reg_idx)
247 {
247 int flatIndex = isa.flattenFloatIndex(reg_idx);
248 int flatIndex = isa->flattenFloatIndex(reg_idx);
248 assert(flatIndex < TheISA::NumFloatRegs);
249 FloatReg regVal = floatRegs.f[flatIndex];
250 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
251 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
252 return regVal;
253 }
254
255 FloatRegBits readFloatRegBits(int reg_idx)
256 {
249 assert(flatIndex < TheISA::NumFloatRegs);
250 FloatReg regVal = floatRegs.f[flatIndex];
251 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
252 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
253 return regVal;
254 }
255
256 FloatRegBits readFloatRegBits(int reg_idx)
257 {
257 int flatIndex = isa.flattenFloatIndex(reg_idx);
258 int flatIndex = isa->flattenFloatIndex(reg_idx);
258 assert(flatIndex < TheISA::NumFloatRegs);
259 FloatRegBits regVal = floatRegs.i[flatIndex];
260 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
261 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
262 return regVal;
263 }
264
265 void setIntReg(int reg_idx, uint64_t val)
266 {
259 assert(flatIndex < TheISA::NumFloatRegs);
260 FloatRegBits regVal = floatRegs.i[flatIndex];
261 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
262 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
263 return regVal;
264 }
265
266 void setIntReg(int reg_idx, uint64_t val)
267 {
267 int flatIndex = isa.flattenIntIndex(reg_idx);
268 int flatIndex = isa->flattenIntIndex(reg_idx);
268 assert(flatIndex < TheISA::NumIntRegs);
269 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
270 reg_idx, flatIndex, val);
271 intRegs[flatIndex] = val;
272 }
273
274 void setFloatReg(int reg_idx, FloatReg val)
275 {
269 assert(flatIndex < TheISA::NumIntRegs);
270 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
271 reg_idx, flatIndex, val);
272 intRegs[flatIndex] = val;
273 }
274
275 void setFloatReg(int reg_idx, FloatReg val)
276 {
276 int flatIndex = isa.flattenFloatIndex(reg_idx);
277 int flatIndex = isa->flattenFloatIndex(reg_idx);
277 assert(flatIndex < TheISA::NumFloatRegs);
278 floatRegs.f[flatIndex] = val;
279 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
280 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
281 }
282
283 void setFloatRegBits(int reg_idx, FloatRegBits val)
284 {
278 assert(flatIndex < TheISA::NumFloatRegs);
279 floatRegs.f[flatIndex] = val;
280 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
281 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
282 }
283
284 void setFloatRegBits(int reg_idx, FloatRegBits val)
285 {
285 int flatIndex = isa.flattenFloatIndex(reg_idx);
286 int flatIndex = isa->flattenFloatIndex(reg_idx);
286 assert(flatIndex < TheISA::NumFloatRegs);
287 // XXX: Fix array out of bounds compiler error for gem5.fast
288 // when checkercpu enabled
289 if (flatIndex < TheISA::NumFloatRegs)
290 floatRegs.i[flatIndex] = val;
291 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
292 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
293 }

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336 void setPredicate(bool val)
337 {
338 predicate = val;
339 }
340
341 MiscReg
342 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
343 {
287 assert(flatIndex < TheISA::NumFloatRegs);
288 // XXX: Fix array out of bounds compiler error for gem5.fast
289 // when checkercpu enabled
290 if (flatIndex < TheISA::NumFloatRegs)
291 floatRegs.i[flatIndex] = val;
292 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
293 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
294 }

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337 void setPredicate(bool val)
338 {
339 predicate = val;
340 }
341
342 MiscReg
343 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
344 {
344 return isa.readMiscRegNoEffect(misc_reg);
345 return isa->readMiscRegNoEffect(misc_reg);
345 }
346
347 MiscReg
348 readMiscReg(int misc_reg, ThreadID tid = 0)
349 {
346 }
347
348 MiscReg
349 readMiscReg(int misc_reg, ThreadID tid = 0)
350 {
350 return isa.readMiscReg(misc_reg, tc);
351 return isa->readMiscReg(misc_reg, tc);
351 }
352
353 void
354 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
355 {
352 }
353
354 void
355 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
356 {
356 return isa.setMiscRegNoEffect(misc_reg, val);
357 return isa->setMiscRegNoEffect(misc_reg, val);
357 }
358
359 void
360 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
361 {
358 }
359
360 void
361 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
362 {
362 return isa.setMiscReg(misc_reg, val, tc);
363 return isa->setMiscReg(misc_reg, val, tc);
363 }
364
365 int
366 flattenIntIndex(int reg)
367 {
364 }
365
366 int
367 flattenIntIndex(int reg)
368 {
368 return isa.flattenIntIndex(reg);
369 return isa->flattenIntIndex(reg);
369 }
370
371 int
372 flattenFloatIndex(int reg)
373 {
370 }
371
372 int
373 flattenFloatIndex(int reg)
374 {
374 return isa.flattenFloatIndex(reg);
375 return isa->flattenFloatIndex(reg);
375 }
376
377 unsigned readStCondFailures() { return storeCondFailures; }
378
379 void setStCondFailures(unsigned sc_failures)
380 { storeCondFailures = sc_failures; }
381
382 void syscall(int64_t callnum)

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377
378 unsigned readStCondFailures() { return storeCondFailures; }
379
380 void setStCondFailures(unsigned sc_failures)
381 { storeCondFailures = sc_failures; }
382
383 void syscall(int64_t callnum)

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