simple_thread.hh (8902:75b524b64c28) simple_thread.hh (9020:14321ce30881)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39 *
40 * Authors: Steve Reinhardt
41 * Nathan Binkert
42 */
43
44#ifndef __CPU_SIMPLE_THREAD_HH__
45#define __CPU_SIMPLE_THREAD_HH__
46
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39 *
40 * Authors: Steve Reinhardt
41 * Nathan Binkert
42 */
43
44#ifndef __CPU_SIMPLE_THREAD_HH__
45#define __CPU_SIMPLE_THREAD_HH__
46
47#include "arch/decoder.hh"
47#include "arch/isa.hh"
48#include "arch/isa_traits.hh"
49#include "arch/registers.hh"
50#include "arch/tlb.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
48#include "arch/isa.hh"
49#include "arch/isa_traits.hh"
50#include "arch/registers.hh"
51#include "arch/tlb.hh"
52#include "arch/types.hh"
53#include "base/types.hh"
54#include "config/the_isa.hh"
54#include "cpu/decode.hh"
55#include "cpu/thread_context.hh"
56#include "cpu/thread_state.hh"
57#include "debug/FloatRegs.hh"
58#include "debug/IntRegs.hh"
59#include "mem/page_table.hh"
60#include "mem/request.hh"
61#include "sim/byteswap.hh"
62#include "sim/eventq.hh"

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123
124 ProxyThreadContext<SimpleThread> *tc;
125
126 System *system;
127
128 TheISA::TLB *itb;
129 TheISA::TLB *dtb;
130
55#include "cpu/thread_context.hh"
56#include "cpu/thread_state.hh"
57#include "debug/FloatRegs.hh"
58#include "debug/IntRegs.hh"
59#include "mem/page_table.hh"
60#include "mem/request.hh"
61#include "sim/byteswap.hh"
62#include "sim/eventq.hh"

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123
124 ProxyThreadContext<SimpleThread> *tc;
125
126 System *system;
127
128 TheISA::TLB *itb;
129 TheISA::TLB *dtb;
130
131 Decoder decoder;
131 TheISA::Decoder decoder;
132
133 // constructor: initialize SimpleThread from given process structure
134 // FS
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb,
137 bool use_kernel_stats = true);
138 // SE
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,

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194 BaseCPU *getCpuPtr() { return baseCpu; }
195
196 TheISA::TLB *getITBPtr() { return itb; }
197
198 TheISA::TLB *getDTBPtr() { return dtb; }
199
200 CheckerCPU *getCheckerCpuPtr() { return NULL; }
201
132
133 // constructor: initialize SimpleThread from given process structure
134 // FS
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb,
137 bool use_kernel_stats = true);
138 // SE
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,

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194 BaseCPU *getCpuPtr() { return baseCpu; }
195
196 TheISA::TLB *getITBPtr() { return itb; }
197
198 TheISA::TLB *getDTBPtr() { return dtb; }
199
200 CheckerCPU *getCheckerCpuPtr() { return NULL; }
201
202 Decoder *getDecoderPtr() { return &decoder; }
202 TheISA::Decoder *getDecoderPtr() { return &decoder; }
203
204 System *getSystemPtr() { return system; }
205
206 Status status() const { return _status; }
207
208 void setStatus(Status newStatus) { _status = newStatus; }
209
210 /// Set the status to Active. Optional delay indicates number of

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204 System *getSystemPtr() { return system; }
205
206 Status status() const { return _status; }
207
208 void setStatus(Status newStatus) { _status = newStatus; }
209
210 /// Set the status to Active. Optional delay indicates number of

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