simple_thread.hh (8852:c744483edfcf) simple_thread.hh (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46
47#include "arch/isa.hh"
48#include "arch/isa_traits.hh"
49#include "arch/registers.hh"
50#include "arch/tlb.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46
47#include "arch/isa.hh"
48#include "arch/isa_traits.hh"
49#include "arch/registers.hh"
50#include "arch/tlb.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54#include "config/use_checker.hh"
55#include "cpu/decode.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/FloatRegs.hh"
59#include "debug/IntRegs.hh"
60#include "mem/page_table.hh"
61#include "mem/request.hh"
62#include "sim/byteswap.hh"
63#include "sim/eventq.hh"
64#include "sim/process.hh"
65#include "sim/serialize.hh"
66#include "sim/system.hh"
67
68class BaseCPU;
54#include "cpu/decode.hh"
55#include "cpu/thread_context.hh"
56#include "cpu/thread_state.hh"
57#include "debug/FloatRegs.hh"
58#include "debug/IntRegs.hh"
59#include "mem/page_table.hh"
60#include "mem/request.hh"
61#include "sim/byteswap.hh"
62#include "sim/eventq.hh"
63#include "sim/process.hh"
64#include "sim/serialize.hh"
65#include "sim/system.hh"
66
67class BaseCPU;
68class CheckerCPU;
69
69
70
71class FunctionProfile;
72class ProfileNode;
73
74namespace TheISA {
75 namespace Kernel {
76 class Statistics;
77 };
78};

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193 ******************************************/
194
195 BaseCPU *getCpuPtr() { return baseCpu; }
196
197 TheISA::TLB *getITBPtr() { return itb; }
198
199 TheISA::TLB *getDTBPtr() { return dtb; }
200
70class FunctionProfile;
71class ProfileNode;
72
73namespace TheISA {
74 namespace Kernel {
75 class Statistics;
76 };
77};

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192 ******************************************/
193
194 BaseCPU *getCpuPtr() { return baseCpu; }
195
196 TheISA::TLB *getITBPtr() { return itb; }
197
198 TheISA::TLB *getDTBPtr() { return dtb; }
199
201#if USE_CHECKER
202 BaseCPU *getCheckerCpuPtr() { return NULL; }
203#endif
200 CheckerCPU *getCheckerCpuPtr() { return NULL; }
204
205 Decoder *getDecoderPtr() { return &decoder; }
206
207 System *getSystemPtr() { return system; }
208
209 Status status() const { return _status; }
210
211 void setStatus(Status newStatus) { _status = newStatus; }

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302 }
303
304 void
305 pcState(const TheISA::PCState &val)
306 {
307 _pcState = val;
308 }
309
201
202 Decoder *getDecoderPtr() { return &decoder; }
203
204 System *getSystemPtr() { return system; }
205
206 Status status() const { return _status; }
207
208 void setStatus(Status newStatus) { _status = newStatus; }

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299 }
300
301 void
302 pcState(const TheISA::PCState &val)
303 {
304 _pcState = val;
305 }
306
310#if USE_CHECKER
311 void
312 pcStateNoRecord(const TheISA::PCState &val)
313 {
314 _pcState = val;
315 }
307 void
308 pcStateNoRecord(const TheISA::PCState &val)
309 {
310 _pcState = val;
311 }
316#endif
317
318 Addr
319 instAddr()
320 {
321 return _pcState.instAddr();
322 }
323
324 Addr

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313 Addr
314 instAddr()
315 {
316 return _pcState.instAddr();
317 }
318
319 Addr

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