simple_thread.hh (8794:e2ac2b7164dd) | simple_thread.hh (8799:dac1e33e07b0) |
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1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 43 unchanged lines hidden (view full) --- 52#include "sim/serialize.hh" 53#include "sim/system.hh" 54 55class BaseCPU; 56 57 58class FunctionProfile; 59class ProfileNode; | 1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 43 unchanged lines hidden (view full) --- 52#include "sim/serialize.hh" 53#include "sim/system.hh" 54 55class BaseCPU; 56 57 58class FunctionProfile; 59class ProfileNode; |
60class FunctionalPort; | |
61class PhysicalPort; 62class TranslatingPort; 63 64namespace TheISA { 65 namespace Kernel { 66 class Statistics; 67 }; 68}; --- 121 unchanged lines hidden (view full) --- 190 TheISA::TLB *getITBPtr() { return itb; } 191 192 TheISA::TLB *getDTBPtr() { return dtb; } 193 194 Decoder *getDecoderPtr() { return &decoder; } 195 196 System *getSystemPtr() { return system; } 197 | 60class PhysicalPort; 61class TranslatingPort; 62 63namespace TheISA { 64 namespace Kernel { 65 class Statistics; 66 }; 67}; --- 121 unchanged lines hidden (view full) --- 189 TheISA::TLB *getITBPtr() { return itb; } 190 191 TheISA::TLB *getDTBPtr() { return dtb; } 192 193 Decoder *getDecoderPtr() { return &decoder; } 194 195 System *getSystemPtr() { return system; } 196 |
198 FunctionalPort *getPhysPort() { return physPort; } | 197 PortProxy* getPhysProxy() { return physProxy; } |
199 200 /** Return a virtual port. This port cannot be cached locally in an object. 201 * After a CPU switch it may point to the wrong memory object which could 202 * mean stale data. 203 */ | 198 199 /** Return a virtual port. This port cannot be cached locally in an object. 200 * After a CPU switch it may point to the wrong memory object which could 201 * mean stale data. 202 */ |
204 VirtualPort *getVirtPort() { return virtPort; } | 203 FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } |
205 206 Status status() const { return _status; } 207 208 void setStatus(Status newStatus) { _status = newStatus; } 209 210 /// Set the status to Active. Optional delay indicates number of 211 /// cycles to wait before beginning execution. 212 void activate(int delay = 1); --- 175 unchanged lines hidden --- | 204 205 Status status() const { return _status; } 206 207 void setStatus(Status newStatus) { _status = newStatus; } 208 209 /// Set the status to Active. Optional delay indicates number of 210 /// cycles to wait before beginning execution. 211 void activate(int delay = 1); --- 175 unchanged lines hidden --- |