simple_thread.hh (6315:c7295a4826d5) simple_thread.hh (6316:51f3026d4cbb)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/regfile.hh"
38#include "arch/tlb.hh"
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/regfile.hh"
38#include "arch/tlb.hh"
39#include "arch/types.hh"
39#include "base/types.hh"
40#include "config/full_system.hh"
41#include "cpu/thread_context.hh"
42#include "cpu/thread_state.hh"
43#include "mem/request.hh"
44#include "sim/byteswap.hh"
45#include "sim/eventq.hh"
46#include "sim/serialize.hh"

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98 typedef ThreadContext::Status Status;
99
100 protected:
101 RegFile regs; // correct-path register context
102 union {
103 FloatReg f[TheISA::NumFloatRegs];
104 FloatRegBits i[TheISA::NumFloatRegs];
105 } floatRegs;
40#include "base/types.hh"
41#include "config/full_system.hh"
42#include "cpu/thread_context.hh"
43#include "cpu/thread_state.hh"
44#include "mem/request.hh"
45#include "sim/byteswap.hh"
46#include "sim/eventq.hh"
47#include "sim/serialize.hh"

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99 typedef ThreadContext::Status Status;
100
101 protected:
102 RegFile regs; // correct-path register context
103 union {
104 FloatReg f[TheISA::NumFloatRegs];
105 FloatRegBits i[TheISA::NumFloatRegs];
106 } floatRegs;
107 TheISA::IntReg intRegs[TheISA::NumIntRegs];
106 TheISA::ISA isa; // one "instance" of the current ISA.
107
108 public:
109 // pointer to CPU associated with this SimpleThread
110 BaseCPU *cpu;
111
112 ProxyThreadContext<SimpleThread> *tc;
113

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225 return NoFault;
226 }
227
228 void copyArchRegs(ThreadContext *tc);
229
230 void clearArchRegs()
231 {
232 regs.clear();
108 TheISA::ISA isa; // one "instance" of the current ISA.
109
110 public:
111 // pointer to CPU associated with this SimpleThread
112 BaseCPU *cpu;
113
114 ProxyThreadContext<SimpleThread> *tc;
115

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227 return NoFault;
228 }
229
230 void copyArchRegs(ThreadContext *tc);
231
232 void clearArchRegs()
233 {
234 regs.clear();
235 memset(intRegs, 0, sizeof(intRegs));
233 memset(floatRegs.i, 0, sizeof(floatRegs.i));
234 }
235
236 //
237 // New accessors for new decoder.
238 //
239 uint64_t readIntReg(int reg_idx)
240 {
241 int flatIndex = isa.flattenIntIndex(reg_idx);
236 memset(floatRegs.i, 0, sizeof(floatRegs.i));
237 }
238
239 //
240 // New accessors for new decoder.
241 //
242 uint64_t readIntReg(int reg_idx)
243 {
244 int flatIndex = isa.flattenIntIndex(reg_idx);
242 return regs.readIntReg(flatIndex);
245 return intRegs[flatIndex];
243 }
244
245 FloatReg readFloatReg(int reg_idx)
246 {
247 int flatIndex = isa.flattenFloatIndex(reg_idx);
248 return floatRegs.f[flatIndex];
249 }
250
251 FloatRegBits readFloatRegBits(int reg_idx)
252 {
253 int flatIndex = isa.flattenFloatIndex(reg_idx);
254 return floatRegs.i[flatIndex];
255 }
256
257 void setIntReg(int reg_idx, uint64_t val)
258 {
259 int flatIndex = isa.flattenIntIndex(reg_idx);
246 }
247
248 FloatReg readFloatReg(int reg_idx)
249 {
250 int flatIndex = isa.flattenFloatIndex(reg_idx);
251 return floatRegs.f[flatIndex];
252 }
253
254 FloatRegBits readFloatRegBits(int reg_idx)
255 {
256 int flatIndex = isa.flattenFloatIndex(reg_idx);
257 return floatRegs.i[flatIndex];
258 }
259
260 void setIntReg(int reg_idx, uint64_t val)
261 {
262 int flatIndex = isa.flattenIntIndex(reg_idx);
260 regs.setIntReg(flatIndex, val);
263 intRegs[flatIndex] = val;
261 }
262
263 void setFloatReg(int reg_idx, FloatReg val)
264 {
265 int flatIndex = isa.flattenFloatIndex(reg_idx);
266 floatRegs.f[flatIndex] = val;
267 }
268

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265
266 void setFloatReg(int reg_idx, FloatReg val)
267 {
268 int flatIndex = isa.flattenFloatIndex(reg_idx);
269 floatRegs.f[flatIndex] = val;
270 }
271

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