simple_thread.hh (6221:58a3c04e6344) | simple_thread.hh (6313:95f69a436c82) |
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1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 | 1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 |
35#include "arch/isa.hh" |
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35#include "arch/isa_traits.hh" 36#include "arch/regfile.hh" 37#include "arch/tlb.hh" 38#include "base/types.hh" 39#include "config/full_system.hh" 40#include "cpu/thread_context.hh" 41#include "cpu/thread_state.hh" 42#include "mem/request.hh" --- 42 unchanged lines hidden (view full) --- 85 * examples. 86 */ 87 88class SimpleThread : public ThreadState 89{ 90 protected: 91 typedef TheISA::RegFile RegFile; 92 typedef TheISA::MachInst MachInst; | 36#include "arch/isa_traits.hh" 37#include "arch/regfile.hh" 38#include "arch/tlb.hh" 39#include "base/types.hh" 40#include "config/full_system.hh" 41#include "cpu/thread_context.hh" 42#include "cpu/thread_state.hh" 43#include "mem/request.hh" --- 42 unchanged lines hidden (view full) --- 86 * examples. 87 */ 88 89class SimpleThread : public ThreadState 90{ 91 protected: 92 typedef TheISA::RegFile RegFile; 93 typedef TheISA::MachInst MachInst; |
93 typedef TheISA::MiscRegFile MiscRegFile; | |
94 typedef TheISA::MiscReg MiscReg; 95 typedef TheISA::FloatReg FloatReg; 96 typedef TheISA::FloatRegBits FloatRegBits; 97 public: 98 typedef ThreadContext::Status Status; 99 100 protected: 101 RegFile regs; // correct-path register context | 94 typedef TheISA::MiscReg MiscReg; 95 typedef TheISA::FloatReg FloatReg; 96 typedef TheISA::FloatRegBits FloatRegBits; 97 public: 98 typedef ThreadContext::Status Status; 99 100 protected: 101 RegFile regs; // correct-path register context |
102 TheISA::ISA isa; // one "instance" of the current ISA. |
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102 103 public: 104 // pointer to CPU associated with this SimpleThread 105 BaseCPU *cpu; 106 107 ProxyThreadContext<SimpleThread> *tc; 108 109 System *system; --- 49 unchanged lines hidden (view full) --- 159 } 160 161 void demapDataPage(Addr vaddr, uint64_t asn) 162 { 163 dtb->demapPage(vaddr, asn); 164 } 165 166#if FULL_SYSTEM | 103 104 public: 105 // pointer to CPU associated with this SimpleThread 106 BaseCPU *cpu; 107 108 ProxyThreadContext<SimpleThread> *tc; 109 110 System *system; --- 49 unchanged lines hidden (view full) --- 160 } 161 162 void demapDataPage(Addr vaddr, uint64_t asn) 163 { 164 dtb->demapPage(vaddr, asn); 165 } 166 167#if FULL_SYSTEM |
167 int getInstAsid() { return regs.instAsid(); } 168 int getDataAsid() { return regs.dataAsid(); } | 168 int getInstAsid() { return isa.instAsid(); } 169 int getDataAsid() { return isa.dataAsid(); } |
169 170 void dumpFuncProfile(); 171 172 Fault hwrei(); 173 174 bool simPalCheck(int palFunc); 175 176#endif --- 47 unchanged lines hidden (view full) --- 224 225 void clearArchRegs() { regs.clear(); } 226 227 // 228 // New accessors for new decoder. 229 // 230 uint64_t readIntReg(int reg_idx) 231 { | 170 171 void dumpFuncProfile(); 172 173 Fault hwrei(); 174 175 bool simPalCheck(int palFunc); 176 177#endif --- 47 unchanged lines hidden (view full) --- 225 226 void clearArchRegs() { regs.clear(); } 227 228 // 229 // New accessors for new decoder. 230 // 231 uint64_t readIntReg(int reg_idx) 232 { |
232 int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); | 233 int flatIndex = isa.flattenIntIndex(reg_idx); |
233 return regs.readIntReg(flatIndex); 234 } 235 236 FloatReg readFloatReg(int reg_idx, int width) 237 { | 234 return regs.readIntReg(flatIndex); 235 } 236 237 FloatReg readFloatReg(int reg_idx, int width) 238 { |
238 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); | 239 int flatIndex = isa.flattenFloatIndex(reg_idx); |
239 return regs.readFloatReg(flatIndex, width); 240 } 241 242 FloatReg readFloatReg(int reg_idx) 243 { | 240 return regs.readFloatReg(flatIndex, width); 241 } 242 243 FloatReg readFloatReg(int reg_idx) 244 { |
244 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); | 245 int flatIndex = isa.flattenFloatIndex(reg_idx); |
245 return regs.readFloatReg(flatIndex); 246 } 247 248 FloatRegBits readFloatRegBits(int reg_idx, int width) 249 { | 246 return regs.readFloatReg(flatIndex); 247 } 248 249 FloatRegBits readFloatRegBits(int reg_idx, int width) 250 { |
250 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); | 251 int flatIndex = isa.flattenFloatIndex(reg_idx); |
251 return regs.readFloatRegBits(flatIndex, width); 252 } 253 254 FloatRegBits readFloatRegBits(int reg_idx) 255 { | 252 return regs.readFloatRegBits(flatIndex, width); 253 } 254 255 FloatRegBits readFloatRegBits(int reg_idx) 256 { |
256 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); | 257 int flatIndex = isa.flattenFloatIndex(reg_idx); |
257 return regs.readFloatRegBits(flatIndex); 258 } 259 260 void setIntReg(int reg_idx, uint64_t val) 261 { | 258 return regs.readFloatRegBits(flatIndex); 259 } 260 261 void setIntReg(int reg_idx, uint64_t val) 262 { |
262 int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); | 263 int flatIndex = isa.flattenIntIndex(reg_idx); |
263 regs.setIntReg(flatIndex, val); 264 } 265 266 void setFloatReg(int reg_idx, FloatReg val, int width) 267 { | 264 regs.setIntReg(flatIndex, val); 265 } 266 267 void setFloatReg(int reg_idx, FloatReg val, int width) 268 { |
268 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); | 269 int flatIndex = isa.flattenFloatIndex(reg_idx); |
269 regs.setFloatReg(flatIndex, val, width); 270 } 271 272 void setFloatReg(int reg_idx, FloatReg val) 273 { | 270 regs.setFloatReg(flatIndex, val, width); 271 } 272 273 void setFloatReg(int reg_idx, FloatReg val) 274 { |
274 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); | 275 int flatIndex = isa.flattenFloatIndex(reg_idx); |
275 regs.setFloatReg(flatIndex, val); 276 } 277 278 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 279 { | 276 regs.setFloatReg(flatIndex, val); 277 } 278 279 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 280 { |
280 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); | 281 int flatIndex = isa.flattenFloatIndex(reg_idx); |
281 regs.setFloatRegBits(flatIndex, val, width); 282 } 283 284 void setFloatRegBits(int reg_idx, FloatRegBits val) 285 { | 282 regs.setFloatRegBits(flatIndex, val, width); 283 } 284 285 void setFloatRegBits(int reg_idx, FloatRegBits val) 286 { |
286 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); | 287 int flatIndex = isa.flattenFloatIndex(reg_idx); |
287 regs.setFloatRegBits(flatIndex, val); 288 } 289 290 uint64_t readPC() 291 { 292 return regs.readPC(); 293 } 294 --- 40 unchanged lines hidden (view full) --- 335 void setNextNPC(uint64_t val) 336 { 337 regs.setNextNPC(val); 338 } 339 340 MiscReg 341 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 342 { | 288 regs.setFloatRegBits(flatIndex, val); 289 } 290 291 uint64_t readPC() 292 { 293 return regs.readPC(); 294 } 295 --- 40 unchanged lines hidden (view full) --- 336 void setNextNPC(uint64_t val) 337 { 338 regs.setNextNPC(val); 339 } 340 341 MiscReg 342 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 343 { |
343 return regs.readMiscRegNoEffect(misc_reg); | 344 return isa.readMiscRegNoEffect(misc_reg); |
344 } 345 346 MiscReg 347 readMiscReg(int misc_reg, ThreadID tid = 0) 348 { | 345 } 346 347 MiscReg 348 readMiscReg(int misc_reg, ThreadID tid = 0) 349 { |
349 return regs.readMiscReg(misc_reg, tc); | 350 return isa.readMiscReg(misc_reg, tc); |
350 } 351 352 void 353 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 354 { | 351 } 352 353 void 354 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 355 { |
355 return regs.setMiscRegNoEffect(misc_reg, val); | 356 return isa.setMiscRegNoEffect(misc_reg, val); |
356 } 357 358 void 359 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 360 { | 357 } 358 359 void 360 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 361 { |
361 return regs.setMiscReg(misc_reg, val, tc); | 362 return isa.setMiscReg(misc_reg, val, tc); |
362 } 363 | 363 } 364 |
365 int 366 flattenIntIndex(int reg) 367 { 368 return isa.flattenIntIndex(reg); 369 } 370 371 int 372 flattenFloatIndex(int reg) 373 { 374 return isa.flattenFloatIndex(reg); 375 } 376 |
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364 unsigned readStCondFailures() { return storeCondFailures; } 365 366 void setStCondFailures(unsigned sc_failures) 367 { storeCondFailures = sc_failures; } 368 369#if !FULL_SYSTEM 370 void syscall(int64_t callnum) 371 { --- 14 unchanged lines hidden --- | 377 unsigned readStCondFailures() { return storeCondFailures; } 378 379 void setStCondFailures(unsigned sc_failures) 380 { storeCondFailures = sc_failures; } 381 382#if !FULL_SYSTEM 383 void syscall(int64_t callnum) 384 { --- 14 unchanged lines hidden --- |