simple_thread.hh (5715:e8c1d4e669a7) simple_thread.hh (5779:c0d731772342)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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380
381 void setStCondFailures(unsigned sc_failures)
382 { storeCondFailures = sc_failures; }
383
384#if !FULL_SYSTEM
385 TheISA::IntReg getSyscallArg(int i)
386 {
387 assert(i < TheISA::NumArgumentRegs);
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 371 unchanged lines hidden (view full) ---

380
381 void setStCondFailures(unsigned sc_failures)
382 { storeCondFailures = sc_failures; }
383
384#if !FULL_SYSTEM
385 TheISA::IntReg getSyscallArg(int i)
386 {
387 assert(i < TheISA::NumArgumentRegs);
388 return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
389 TheISA::ArgumentReg[i]));
388 TheISA::IntReg val = regs.readIntReg(
389 TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i]));
390#if THE_ISA == SPARC_ISA
391 if (bits(this->readMiscRegNoEffect(
392 SparcISA::MISCREG_PSTATE), 3, 3)) {
393 val = bits(val, 31, 0);
394 }
395#endif
396 return val;
390 }
391
392 // used to shift args for indirect syscall
393 void setSyscallArg(int i, TheISA::IntReg val)
394 {
395 assert(i < TheISA::NumArgumentRegs);
396 regs.setIntReg(TheISA::flattenIntIndex(getTC(),
397 TheISA::ArgumentReg[i]), val);

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397 }
398
399 // used to shift args for indirect syscall
400 void setSyscallArg(int i, TheISA::IntReg val)
401 {
402 assert(i < TheISA::NumArgumentRegs);
403 regs.setIntReg(TheISA::flattenIntIndex(getTC(),
404 TheISA::ArgumentReg[i]), val);

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