simple_thread.hh (5088:2d5e28510f27) simple_thread.hh (5222:bb733a878f85)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 354 unchanged lines hidden (view full) ---

363 return regs.setMiscReg(misc_reg, val, tc);
364 }
365
366 unsigned readStCondFailures() { return storeCondFailures; }
367
368 void setStCondFailures(unsigned sc_failures)
369 { storeCondFailures = sc_failures; }
370
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 354 unchanged lines hidden (view full) ---

363 return regs.setMiscReg(misc_reg, val, tc);
364 }
365
366 unsigned readStCondFailures() { return storeCondFailures; }
367
368 void setStCondFailures(unsigned sc_failures)
369 { storeCondFailures = sc_failures; }
370
371 void setShadowSet(int css, int tid=0) {
372 regs.setShadowSet(css);
373 }
374
371#if !FULL_SYSTEM
372 TheISA::IntReg getSyscallArg(int i)
373 {
374 assert(i < TheISA::NumArgumentRegs);
375 return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
376 TheISA::ArgumentReg[i]));
377 }
378

--- 35 unchanged lines hidden --- 		375#if !FULL_SYSTEM
376 TheISA::IntReg getSyscallArg(int i)
377 {
378 assert(i < TheISA::NumArgumentRegs);
379 return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
380 TheISA::ArgumentReg[i]));
381 }
382

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