simple_thread.hh (3776:4f88e76d8ebe) simple_thread.hh (3791:f1783bae1afe)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 220 unchanged lines hidden (view full) ---

229 void suspend();
230
231 /// Set the status to Unallocated.
232 void deallocate();
233
234 /// Set the status to Halted.
235 void halt();
236
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 220 unchanged lines hidden (view full) ---

229 void suspend();
230
231 /// Set the status to Unallocated.
232 void deallocate();
233
234 /// Set the status to Halted.
235 void halt();
236
237/*
238 template <class T>
239 Fault read(RequestPtr &req, T &data)
240 {
241#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
242 if (req->isLocked()) {
243 req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
244 req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
245 }
246#endif
247
248 Fault error;
249 error = mem->prot_read(req->paddr, data, req->size);
250 data = LittleEndianGuest::gtoh(data);
251 return error;
252 }
253
254 template <class T>
255 Fault write(RequestPtr &req, T &data)
256 {
257#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
258 ExecContext *xc;
259
260 // If this is a store conditional, act appropriately
261 if (req->isLocked()) {
262 xc = req->xc;
263
264 if (req->isUncacheable()) {
265 // Don't update result register (see stq_c in isa_desc)
266 req->result = 2;
267 xc->setStCondFailures(0);//Needed? [RGD]
268 } else {
269 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
270 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
271 req->result = lock_flag;
272 if (!lock_flag ||
273 ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
274 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
275 xc->setStCondFailures(xc->readStCondFailures() + 1);
276 if (((xc->readStCondFailures()) % 100000) == 0) {
277 std::cerr << "Warning: "
278 << xc->readStCondFailures()
279 << " consecutive store conditional failures "
280 << "on cpu " << req->xc->readCpuId()
281 << std::endl;
282 }
283 return NoFault;
284 }
285 else xc->setStCondFailures(0);
286 }
287 }
288
289 // Need to clear any locked flags on other proccessors for
290 // this address. Only do this for succsful Store Conditionals
291 // and all other stores (WH64?). Unsuccessful Store
292 // Conditionals would have returned above, and wouldn't fall
293 // through.
294 for (int i = 0; i < system->execContexts.size(); i++){
295 xc = system->execContexts[i];
296 if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
297 (req->paddr & ~0xf)) {
298 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
299 }
300 }
301
302#endif
303 return mem->prot_write(req->paddr, (T)htog(data), req->size);
304 }
305*/
306 virtual bool misspeculating();
307
308 Fault instRead(RequestPtr &req)
309 {
310 panic("instRead not implemented");
311 // return funcPhysMem->read(req, inst);
312 return NoFault;
313 }

--- 174 unchanged lines hidden --- 		237 virtual bool misspeculating();
238
239 Fault instRead(RequestPtr &req)
240 {
241 panic("instRead not implemented");
242 // return funcPhysMem->read(req, inst);
243 return NoFault;
244 }

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