simple_thread.hh (3733:2e34561f1eba) simple_thread.hh (3776:4f88e76d8ebe)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa_traits.hh"
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/regfile.hh"
37#include "arch/syscallreturn.hh"
36#include "config/full_system.hh"
37#include "cpu/thread_context.hh"
38#include "cpu/thread_state.hh"
39#include "mem/physical.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/eventq.hh"
43#include "sim/host.hh"

--- 183 unchanged lines hidden (view full) ---

227 void suspend();
228
229 /// Set the status to Unallocated.
230 void deallocate();
231
232 /// Set the status to Halted.
233 void halt();
234
38#include "config/full_system.hh"
39#include "cpu/thread_context.hh"
40#include "cpu/thread_state.hh"
41#include "mem/physical.hh"
42#include "mem/request.hh"
43#include "sim/byteswap.hh"
44#include "sim/eventq.hh"
45#include "sim/host.hh"

--- 183 unchanged lines hidden (view full) ---

229 void suspend();
230
231 /// Set the status to Unallocated.
232 void deallocate();
233
234 /// Set the status to Halted.
235 void halt();
236
237/*
238 template <class T>
239 Fault read(RequestPtr &req, T &data)
240 {
241#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
242 if (req->isLocked()) {
243 req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
244 req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
245 }
246#endif
247
248 Fault error;
249 error = mem->prot_read(req->paddr, data, req->size);
250 data = LittleEndianGuest::gtoh(data);
251 return error;
252 }
253
254 template <class T>
255 Fault write(RequestPtr &req, T &data)
256 {
257#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
258 ExecContext *xc;
259
260 // If this is a store conditional, act appropriately
261 if (req->isLocked()) {
262 xc = req->xc;
263
264 if (req->isUncacheable()) {
265 // Don't update result register (see stq_c in isa_desc)
266 req->result = 2;
267 xc->setStCondFailures(0);//Needed? [RGD]
268 } else {
269 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
270 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
271 req->result = lock_flag;
272 if (!lock_flag ||
273 ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
274 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
275 xc->setStCondFailures(xc->readStCondFailures() + 1);
276 if (((xc->readStCondFailures()) % 100000) == 0) {
277 std::cerr << "Warning: "
278 << xc->readStCondFailures()
279 << " consecutive store conditional failures "
280 << "on cpu " << req->xc->readCpuId()
281 << std::endl;
282 }
283 return NoFault;
284 }
285 else xc->setStCondFailures(0);
286 }
287 }
288
289 // Need to clear any locked flags on other proccessors for
290 // this address. Only do this for succsful Store Conditionals
291 // and all other stores (WH64?). Unsuccessful Store
292 // Conditionals would have returned above, and wouldn't fall
293 // through.
294 for (int i = 0; i < system->execContexts.size(); i++){
295 xc = system->execContexts[i];
296 if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
297 (req->paddr & ~0xf)) {
298 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
299 }
300 }
301
302#endif
303 return mem->prot_write(req->paddr, (T)htog(data), req->size);
304 }
305*/
235 virtual bool misspeculating();
236
237 Fault instRead(RequestPtr &req)
238 {
239 panic("instRead not implemented");
240 // return funcPhysMem->read(req, inst);
241 return NoFault;
242 }
243
244 void copyArchRegs(ThreadContext *tc);
245
246 void clearArchRegs() { regs.clear(); }
247
248 //
249 // New accessors for new decoder.
250 //
251 uint64_t readIntReg(int reg_idx)
252 {
306 virtual bool misspeculating();
307
308 Fault instRead(RequestPtr &req)
309 {
310 panic("instRead not implemented");
311 // return funcPhysMem->read(req, inst);
312 return NoFault;
313 }
314
315 void copyArchRegs(ThreadContext *tc);
316
317 void clearArchRegs() { regs.clear(); }
318
319 //
320 // New accessors for new decoder.
321 //
322 uint64_t readIntReg(int reg_idx)
323 {
253 return regs.readIntReg(reg_idx);
324 return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
254 }
255
256 FloatReg readFloatReg(int reg_idx, int width)
257 {
258 return regs.readFloatReg(reg_idx, width);
259 }
260
261 FloatReg readFloatReg(int reg_idx)

--- 8 unchanged lines hidden (view full) ---

270
271 FloatRegBits readFloatRegBits(int reg_idx)
272 {
273 return regs.readFloatRegBits(reg_idx);
274 }
275
276 void setIntReg(int reg_idx, uint64_t val)
277 {
325 }
326
327 FloatReg readFloatReg(int reg_idx, int width)
328 {
329 return regs.readFloatReg(reg_idx, width);
330 }
331
332 FloatReg readFloatReg(int reg_idx)

--- 8 unchanged lines hidden (view full) ---

341
342 FloatRegBits readFloatRegBits(int reg_idx)
343 {
344 return regs.readFloatRegBits(reg_idx);
345 }
346
347 void setIntReg(int reg_idx, uint64_t val)
348 {
278 regs.setIntReg(reg_idx, val);
349 regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
279 }
280
281 void setFloatReg(int reg_idx, FloatReg val, int width)
282 {
283 regs.setFloatReg(reg_idx, val, width);
284 }
285
286 void setFloatReg(int reg_idx, FloatReg val)

--- 84 unchanged lines hidden (view full) ---

371 unsigned readStCondFailures() { return storeCondFailures; }
372
373 void setStCondFailures(unsigned sc_failures)
374 { storeCondFailures = sc_failures; }
375
376#if !FULL_SYSTEM
377 TheISA::IntReg getSyscallArg(int i)
378 {
350 }
351
352 void setFloatReg(int reg_idx, FloatReg val, int width)
353 {
354 regs.setFloatReg(reg_idx, val, width);
355 }
356
357 void setFloatReg(int reg_idx, FloatReg val)

--- 84 unchanged lines hidden (view full) ---

442 unsigned readStCondFailures() { return storeCondFailures; }
443
444 void setStCondFailures(unsigned sc_failures)
445 { storeCondFailures = sc_failures; }
446
447#if !FULL_SYSTEM
448 TheISA::IntReg getSyscallArg(int i)
449 {
379 return regs.readIntReg(TheISA::ArgumentReg0 + i);
450 return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
451 TheISA::ArgumentReg0 + i));
380 }
381
382 // used to shift args for indirect syscall
383 void setSyscallArg(int i, TheISA::IntReg val)
384 {
452 }
453
454 // used to shift args for indirect syscall
455 void setSyscallArg(int i, TheISA::IntReg val)
456 {
385 regs.setIntReg(TheISA::ArgumentReg0 + i, val);
457 regs.setIntReg(TheISA::flattenIntIndex(getTC(),
458 TheISA::ArgumentReg0 + i), val);
386 }
387
388 void setSyscallReturn(SyscallReturn return_value)
389 {
459 }
460
461 void setSyscallReturn(SyscallReturn return_value)
462 {
390 TheISA::setSyscallReturn(return_value, &regs);
463 TheISA::setSyscallReturn(return_value, getTC());
391 }
392
393 void syscall(int64_t callnum)
394 {
395 process->syscall(callnum, tc);
396 }
397#endif
398

--- 16 unchanged lines hidden --- 		464 }
465
466 void syscall(int64_t callnum)
467 {
468 process->syscall(callnum, tc);
469 }
470#endif
471

--- 16 unchanged lines hidden ---