simple_thread.hh (3675:dc883b610345) simple_thread.hh (3733:2e34561f1eba)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 218 unchanged lines hidden (view full) ---

227 void suspend();
228
229 /// Set the status to Unallocated.
230 void deallocate();
231
232 /// Set the status to Halted.
233 void halt();
234
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 218 unchanged lines hidden (view full) ---

227 void suspend();
228
229 /// Set the status to Unallocated.
230 void deallocate();
231
232 /// Set the status to Halted.
233 void halt();
234
235/*
236 template <class T>
237 Fault read(RequestPtr &req, T &data)
238 {
239#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
240 if (req->isLocked()) {
241 req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
242 req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
243 }
244#endif
245
246 Fault error;
247 error = mem->prot_read(req->paddr, data, req->size);
248 data = LittleEndianGuest::gtoh(data);
249 return error;
250 }
251
252 template <class T>
253 Fault write(RequestPtr &req, T &data)
254 {
255#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
256 ExecContext *xc;
257
258 // If this is a store conditional, act appropriately
259 if (req->isLocked()) {
260 xc = req->xc;
261
262 if (req->isUncacheable()) {
263 // Don't update result register (see stq_c in isa_desc)
264 req->result = 2;
265 xc->setStCondFailures(0);//Needed? [RGD]
266 } else {
267 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
268 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
269 req->result = lock_flag;
270 if (!lock_flag ||
271 ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
272 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
273 xc->setStCondFailures(xc->readStCondFailures() + 1);
274 if (((xc->readStCondFailures()) % 100000) == 0) {
275 std::cerr << "Warning: "
276 << xc->readStCondFailures()
277 << " consecutive store conditional failures "
278 << "on cpu " << req->xc->readCpuId()
279 << std::endl;
280 }
281 return NoFault;
282 }
283 else xc->setStCondFailures(0);
284 }
285 }
286
287 // Need to clear any locked flags on other proccessors for
288 // this address. Only do this for succsful Store Conditionals
289 // and all other stores (WH64?). Unsuccessful Store
290 // Conditionals would have returned above, and wouldn't fall
291 // through.
292 for (int i = 0; i < system->execContexts.size(); i++){
293 xc = system->execContexts[i];
294 if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
295 (req->paddr & ~0xf)) {
296 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
297 }
298 }
299
300#endif
301 return mem->prot_write(req->paddr, (T)htog(data), req->size);
302 }
303*/
304 virtual bool misspeculating();
305
306 Fault instRead(RequestPtr &req)
307 {
308 panic("instRead not implemented");
309 // return funcPhysMem->read(req, inst);
310 return NoFault;
311 }

--- 172 unchanged lines hidden --- 		235 virtual bool misspeculating();
236
237 Fault instRead(RequestPtr &req)
238 {
239 panic("instRead not implemented");
240 // return funcPhysMem->read(req, inst);
241 return NoFault;
242 }

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