simple_thread.hh (3490:37a313c96683) simple_thread.hh (3521:0b0b3551def0)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 426 unchanged lines hidden (view full) ---

435 return regs.setMiscRegWithEffect(misc_reg, val, tc);
436 }
437
438 unsigned readStCondFailures() { return storeCondFailures; }
439
440 void setStCondFailures(unsigned sc_failures)
441 { storeCondFailures = sc_failures; }
442
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 426 unchanged lines hidden (view full) ---

435 return regs.setMiscRegWithEffect(misc_reg, val, tc);
436 }
437
438 unsigned readStCondFailures() { return storeCondFailures; }
439
440 void setStCondFailures(unsigned sc_failures)
441 { storeCondFailures = sc_failures; }
442
443#if FULL_SYSTEM
444 bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); }
445#endif
446
447#if !FULL_SYSTEM
448 TheISA::IntReg getSyscallArg(int i)
449 {
450 return regs.readIntReg(TheISA::ArgumentReg0 + i);
451 }
452
453 // used to shift args for indirect syscall
454 void setSyscallArg(int i, TheISA::IntReg val)

--- 31 unchanged lines hidden --- 		443#if !FULL_SYSTEM
444 TheISA::IntReg getSyscallArg(int i)
445 {
446 return regs.readIntReg(TheISA::ArgumentReg0 + i);
447 }
448
449 // used to shift args for indirect syscall
450 void setSyscallArg(int i, TheISA::IntReg val)

--- 31 unchanged lines hidden ---