simple_thread.hh (3485:ac89a047e5b6) simple_thread.hh (3490:37a313c96683)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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102 // pointer to CPU associated with this SimpleThread
103 BaseCPU *cpu;
104
105 ProxyThreadContext<SimpleThread> *tc;
106
107 System *system;
108
109#if FULL_SYSTEM
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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102 // pointer to CPU associated with this SimpleThread
103 BaseCPU *cpu;
104
105 ProxyThreadContext<SimpleThread> *tc;
106
107 System *system;
108
109#if FULL_SYSTEM
110 AlphaITB *itb;
111 AlphaDTB *dtb;
110 TheISA::ITB *itb;
111 TheISA::DTB *dtb;
112#endif
113
114 // constructor: initialize SimpleThread from given process structure
115#if FULL_SYSTEM
116 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
112#endif
113
114 // constructor: initialize SimpleThread from given process structure
115#if FULL_SYSTEM
116 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
117 AlphaITB *_itb, AlphaDTB *_dtb,
117 TheISA::ITB *_itb, TheISA::DTB *_dtb,
118 bool use_kernel_stats = true);
119#else
120 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
121#endif
122
123 SimpleThread();
124
125 virtual ~SimpleThread();

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162
163 Fault translateDataWriteReq(RequestPtr &req)
164 {
165 return dtb->translate(req, tc, true);
166 }
167
168 void dumpFuncProfile();
169
118 bool use_kernel_stats = true);
119#else
120 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
121#endif
122
123 SimpleThread();
124
125 virtual ~SimpleThread();

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162
163 Fault translateDataWriteReq(RequestPtr &req)
164 {
165 return dtb->translate(req, tc, true);
166 }
167
168 void dumpFuncProfile();
169
170 int readIntrFlag() { return regs.intrflag; }
171 void setIntrFlag(int val) { regs.intrflag = val; }
172 Fault hwrei();
173
174 bool simPalCheck(int palFunc);
175#else
176
177 Fault translateInstReq(RequestPtr &req)
178 {
179 return process->pTable->translate(req);

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196
197 BaseCPU *getCpuPtr() { return cpu; }
198
199 int getThreadNum() { return tid; }
200
201#if FULL_SYSTEM
202 System *getSystemPtr() { return system; }
203
170 Fault hwrei();
171
172 bool simPalCheck(int palFunc);
173#else
174
175 Fault translateInstReq(RequestPtr &req)
176 {
177 return process->pTable->translate(req);

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194
195 BaseCPU *getCpuPtr() { return cpu; }
196
197 int getThreadNum() { return tid; }
198
199#if FULL_SYSTEM
200 System *getSystemPtr() { return system; }
201
204 AlphaITB *getITBPtr() { return itb; }
202 TheISA::ITB *getITBPtr() { return itb; }
205
203
206 AlphaDTB *getDTBPtr() { return dtb; }
204 TheISA::DTB *getDTBPtr() { return dtb; }
207
208 FunctionalPort *getPhysPort() { return physPort; }
209
210 /** Return a virtual port. If no thread context is specified then a static
211 * port is returned. Otherwise a port is created and returned. It must be
212 * deleted by deleteVirtPort(). */
213 VirtualPort *getVirtPort(ThreadContext *tc);
214

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417 regs.setNextNPC(val);
418 }
419
420 MiscReg readMiscReg(int misc_reg)
421 {
422 return regs.readMiscReg(misc_reg);
423 }
424
205
206 FunctionalPort *getPhysPort() { return physPort; }
207
208 /** Return a virtual port. If no thread context is specified then a static
209 * port is returned. Otherwise a port is created and returned. It must be
210 * deleted by deleteVirtPort(). */
211 VirtualPort *getVirtPort(ThreadContext *tc);
212

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415 regs.setNextNPC(val);
416 }
417
418 MiscReg readMiscReg(int misc_reg)
419 {
420 return regs.readMiscReg(misc_reg);
421 }
422
425 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
423 MiscReg readMiscRegWithEffect(int misc_reg)
426 {
424 {
427 return regs.readMiscRegWithEffect(misc_reg, fault, tc);
425 return regs.readMiscRegWithEffect(misc_reg, tc);
428 }
429
426 }
427
430 Fault setMiscReg(int misc_reg, const MiscReg &val)
428 void setMiscReg(int misc_reg, const MiscReg &val)
431 {
432 return regs.setMiscReg(misc_reg, val);
433 }
434
429 {
430 return regs.setMiscReg(misc_reg, val);
431 }
432
435 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
433 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
436 {
437 return regs.setMiscRegWithEffect(misc_reg, val, tc);
438 }
439
440 unsigned readStCondFailures() { return storeCondFailures; }
441
442 void setStCondFailures(unsigned sc_failures)
443 { storeCondFailures = sc_failures; }

--- 44 unchanged lines hidden --- 		434 {
435 return regs.setMiscRegWithEffect(misc_reg, val, tc);
436 }
437
438 unsigned readStCondFailures() { return storeCondFailures; }
439
440 void setStCondFailures(unsigned sc_failures)
441 { storeCondFailures = sc_failures; }

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