simple_thread.hh (3479:4fbcaa81d105) simple_thread.hh (3485:ac89a047e5b6)
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 93 unchanged lines hidden (view full) ---

102 // pointer to CPU associated with this SimpleThread
103 BaseCPU *cpu;
104
105 ProxyThreadContext<SimpleThread> *tc;
106
107 System *system;
108
109#if FULL_SYSTEM
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 93 unchanged lines hidden (view full) ---

102 // pointer to CPU associated with this SimpleThread
103 BaseCPU *cpu;
104
105 ProxyThreadContext<SimpleThread> *tc;
106
107 System *system;
108
109#if FULL_SYSTEM
110 TheISA::ITB *itb;
111 TheISA::DTB *dtb;
110 AlphaITB *itb;
111 AlphaDTB *dtb;
112#endif
113
114 // constructor: initialize SimpleThread from given process structure
115#if FULL_SYSTEM
116 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
112#endif
113
114 // constructor: initialize SimpleThread from given process structure
115#if FULL_SYSTEM
116 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
117 TheISA::ITB *_itb, TheISA::DTB *_dtb,
117 AlphaITB *_itb, AlphaDTB *_dtb,
118 bool use_kernel_stats = true);
119#else
120 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
121#endif
122
123 SimpleThread();
124
125 virtual ~SimpleThread();

--- 36 unchanged lines hidden (view full) ---

162
163 Fault translateDataWriteReq(RequestPtr &req)
164 {
165 return dtb->translate(req, tc, true);
166 }
167
168 void dumpFuncProfile();
169
118 bool use_kernel_stats = true);
119#else
120 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
121#endif
122
123 SimpleThread();
124
125 virtual ~SimpleThread();

--- 36 unchanged lines hidden (view full) ---

162
163 Fault translateDataWriteReq(RequestPtr &req)
164 {
165 return dtb->translate(req, tc, true);
166 }
167
168 void dumpFuncProfile();
169
170 int readIntrFlag() { return regs.intrflag; }
171 void setIntrFlag(int val) { regs.intrflag = val; }
170 Fault hwrei();
171
172 bool simPalCheck(int palFunc);
173#else
172 Fault hwrei();
173
174 bool simPalCheck(int palFunc);
175#else
174 // Override this function.
175 TranslatingPort *getMemPort();
176
177 Fault translateInstReq(RequestPtr &req)
178 {
179 return process->pTable->translate(req);
180 }
181
182 Fault translateDataReadReq(RequestPtr &req)
183 {

--- 12 unchanged lines hidden (view full) ---

196
197 BaseCPU *getCpuPtr() { return cpu; }
198
199 int getThreadNum() { return tid; }
200
201#if FULL_SYSTEM
202 System *getSystemPtr() { return system; }
203
176
177 Fault translateInstReq(RequestPtr &req)
178 {
179 return process->pTable->translate(req);
180 }
181
182 Fault translateDataReadReq(RequestPtr &req)
183 {

--- 12 unchanged lines hidden (view full) ---

196
197 BaseCPU *getCpuPtr() { return cpu; }
198
199 int getThreadNum() { return tid; }
200
201#if FULL_SYSTEM
202 System *getSystemPtr() { return system; }
203
204 TheISA::ITB *getITBPtr() { return itb; }
204 AlphaITB *getITBPtr() { return itb; }
205
205
206 TheISA::DTB *getDTBPtr() { return dtb; }
206 AlphaDTB *getDTBPtr() { return dtb; }
207
208 FunctionalPort *getPhysPort() { return physPort; }
209
210 /** Return a virtual port. If no thread context is specified then a static
211 * port is returned. Otherwise a port is created and returned. It must be
212 * deleted by deleteVirtPort(). */
213 VirtualPort *getVirtPort(ThreadContext *tc);
214

--- 202 unchanged lines hidden (view full) ---

417 regs.setNextNPC(val);
418 }
419
420 MiscReg readMiscReg(int misc_reg)
421 {
422 return regs.readMiscReg(misc_reg);
423 }
424
207
208 FunctionalPort *getPhysPort() { return physPort; }
209
210 /** Return a virtual port. If no thread context is specified then a static
211 * port is returned. Otherwise a port is created and returned. It must be
212 * deleted by deleteVirtPort(). */
213 VirtualPort *getVirtPort(ThreadContext *tc);
214

--- 202 unchanged lines hidden (view full) ---

417 regs.setNextNPC(val);
418 }
419
420 MiscReg readMiscReg(int misc_reg)
421 {
422 return regs.readMiscReg(misc_reg);
423 }
424
425 MiscReg readMiscRegWithEffect(int misc_reg)
425 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
426 {
426 {
427 return regs.readMiscRegWithEffect(misc_reg, tc);
427 return regs.readMiscRegWithEffect(misc_reg, fault, tc);
428 }
429
428 }
429
430 void setMiscReg(int misc_reg, const MiscReg &val)
430 Fault setMiscReg(int misc_reg, const MiscReg &val)
431 {
432 return regs.setMiscReg(misc_reg, val);
433 }
434
431 {
432 return regs.setMiscReg(misc_reg, val);
433 }
434
435 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
435 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
436 {
437 return regs.setMiscRegWithEffect(misc_reg, val, tc);
438 }
439
440 unsigned readStCondFailures() { return storeCondFailures; }
441
442 void setStCondFailures(unsigned sc_failures)
443 { storeCondFailures = sc_failures; }

--- 44 unchanged lines hidden --- 		436 {
437 return regs.setMiscRegWithEffect(misc_reg, val, tc);
438 }
439
440 unsigned readStCondFailures() { return storeCondFailures; }
441
442 void setStCondFailures(unsigned sc_failures)
443 { storeCondFailures = sc_failures; }

--- 44 unchanged lines hidden ---