simple_thread.hh (13693:85fa3a41014b) | simple_thread.hh (13865:cca49fc49c57) |
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1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 69 unchanged lines hidden (view full) --- 78 namespace Kernel { 79 class Statistics; 80 } 81} 82 83/** 84 * The SimpleThread object provides a combination of the ThreadState 85 * object and the ThreadContext interface. It implements the | 1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 69 unchanged lines hidden (view full) --- 78 namespace Kernel { 79 class Statistics; 80 } 81} 82 83/** 84 * The SimpleThread object provides a combination of the ThreadState 85 * object and the ThreadContext interface. It implements the |
86 * ThreadContext interface so that a ProxyThreadContext class can be 87 * made using SimpleThread as the template parameter (see 88 * thread_context.hh). It adds to the ThreadState object by adding all | 86 * ThreadContext interface and adds to the ThreadState object by adding all |
89 * the objects needed for simple functional execution, including a 90 * simple architectural register file, and pointers to the ITB and DTB 91 * in full system mode. For CPU models that do not need more advanced 92 * ways to hold state (i.e. a separate physical register file, or 93 * separate fetch and commit PC's), this SimpleThread class provides 94 * all the necessary state for full architecture-level functional 95 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 96 * examples. 97 */ 98 | 87 * the objects needed for simple functional execution, including a 88 * simple architectural register file, and pointers to the ITB and DTB 89 * in full system mode. For CPU models that do not need more advanced 90 * ways to hold state (i.e. a separate physical register file, or 91 * separate fetch and commit PC's), this SimpleThread class provides 92 * all the necessary state for full architecture-level functional 93 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 94 * examples. 95 */ 96 |
99class SimpleThread : public ThreadState | 97class SimpleThread : public ThreadState, public ThreadContext |
100{ 101 protected: 102 typedef TheISA::MachInst MachInst; 103 using VecRegContainer = TheISA::VecRegContainer; 104 using VecElem = TheISA::VecElem; 105 using VecPredRegContainer = TheISA::VecPredRegContainer; 106 public: 107 typedef ThreadContext::Status Status; --- 11 unchanged lines hidden (view full) --- 119 TheISA::PCState _pcState; 120 121 /** Did this instruction execute or is it predicated false */ 122 bool predicate; 123 124 public: 125 std::string name() const 126 { | 98{ 99 protected: 100 typedef TheISA::MachInst MachInst; 101 using VecRegContainer = TheISA::VecRegContainer; 102 using VecElem = TheISA::VecElem; 103 using VecPredRegContainer = TheISA::VecPredRegContainer; 104 public: 105 typedef ThreadContext::Status Status; --- 11 unchanged lines hidden (view full) --- 117 TheISA::PCState _pcState; 118 119 /** Did this instruction execute or is it predicated false */ 120 bool predicate; 121 122 public: 123 std::string name() const 124 { |
127 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); | 125 return csprintf("%s.[tid:%i]", baseCpu->name(), threadId()); |
128 } 129 | 126 } 127 |
130 ProxyThreadContext<SimpleThread> *tc; 131 | |
132 System *system; 133 134 BaseTLB *itb; 135 BaseTLB *dtb; 136 137 TheISA::Decoder decoder; 138 139 // constructor: initialize SimpleThread from given process structure 140 // FS 141 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 142 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 143 bool use_kernel_stats = true); 144 // SE 145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 146 Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 147 TheISA::ISA *_isa); 148 | 128 System *system; 129 130 BaseTLB *itb; 131 BaseTLB *dtb; 132 133 TheISA::Decoder decoder; 134 135 // constructor: initialize SimpleThread from given process structure 136 // FS 137 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 138 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 139 bool use_kernel_stats = true); 140 // SE 141 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 142 Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 143 TheISA::ISA *_isa); 144 |
149 virtual ~SimpleThread(); | 145 virtual ~SimpleThread() {} |
150 | 146 |
151 virtual void takeOverFrom(ThreadContext *oldContext); | 147 void takeOverFrom(ThreadContext *oldContext) override; |
152 | 148 |
153 void regStats(const std::string &name); | 149 void regStats(const std::string &name) override; |
154 155 void copyState(ThreadContext *oldContext); 156 157 void serialize(CheckpointOut &cp) const override; 158 void unserialize(CheckpointIn &cp) override; 159 void startup(); 160 161 /*************************************************************** 162 * SimpleThread functions to provide CPU with access to various 163 * state. 164 **************************************************************/ 165 166 /** Returns the pointer to this SimpleThread's ThreadContext. Used 167 * when a ThreadContext must be passed to objects outside of the 168 * CPU. 169 */ | 150 151 void copyState(ThreadContext *oldContext); 152 153 void serialize(CheckpointOut &cp) const override; 154 void unserialize(CheckpointIn &cp) override; 155 void startup(); 156 157 /*************************************************************** 158 * SimpleThread functions to provide CPU with access to various 159 * state. 160 **************************************************************/ 161 162 /** Returns the pointer to this SimpleThread's ThreadContext. Used 163 * when a ThreadContext must be passed to objects outside of the 164 * CPU. 165 */ |
170 ThreadContext *getTC() { return tc; } | 166 ThreadContext *getTC() { return this; } |
171 172 void demapPage(Addr vaddr, uint64_t asn) 173 { 174 itb->demapPage(vaddr, asn); 175 dtb->demapPage(vaddr, asn); 176 } 177 178 void demapInstPage(Addr vaddr, uint64_t asn) 179 { 180 itb->demapPage(vaddr, asn); 181 } 182 183 void demapDataPage(Addr vaddr, uint64_t asn) 184 { 185 dtb->demapPage(vaddr, asn); 186 } 187 | 167 168 void demapPage(Addr vaddr, uint64_t asn) 169 { 170 itb->demapPage(vaddr, asn); 171 dtb->demapPage(vaddr, asn); 172 } 173 174 void demapInstPage(Addr vaddr, uint64_t asn) 175 { 176 itb->demapPage(vaddr, asn); 177 } 178 179 void demapDataPage(Addr vaddr, uint64_t asn) 180 { 181 dtb->demapPage(vaddr, asn); 182 } 183 |
188 void dumpFuncProfile(); | 184 void dumpFuncProfile() override; |
189 190 Fault hwrei(); 191 192 bool simPalCheck(int palFunc); 193 194 /******************************************* 195 * ThreadContext interface functions. 196 ******************************************/ 197 | 185 186 Fault hwrei(); 187 188 bool simPalCheck(int palFunc); 189 190 /******************************************* 191 * ThreadContext interface functions. 192 ******************************************/ 193 |
198 BaseCPU *getCpuPtr() { return baseCpu; } | 194 BaseCPU *getCpuPtr() override { return baseCpu; } |
199 | 195 |
200 BaseTLB *getITBPtr() { return itb; } | 196 int cpuId() const override { return ThreadState::cpuId(); } 197 uint32_t socketId() const override { return ThreadState::socketId(); } 198 int threadId() const override { return ThreadState::threadId(); } 199 void setThreadId(int id) override { ThreadState::setThreadId(id); } 200 ContextID contextId() const override { return ThreadState::contextId(); } 201 void setContextId(ContextID id) override { ThreadState::setContextId(id); } |
201 | 202 |
202 BaseTLB *getDTBPtr() { return dtb; } | 203 BaseTLB *getITBPtr() override { return itb; } |
203 | 204 |
204 CheckerCPU *getCheckerCpuPtr() { return NULL; } | 205 BaseTLB *getDTBPtr() override { return dtb; } |
205 | 206 |
206 TheISA::ISA *getIsaPtr() { return isa; } | 207 CheckerCPU *getCheckerCpuPtr() override { return NULL; } |
207 | 208 |
208 TheISA::Decoder *getDecoderPtr() { return &decoder; } | 209 TheISA::ISA *getIsaPtr() override { return isa; } |
209 | 210 |
210 System *getSystemPtr() { return system; } | 211 TheISA::Decoder *getDecoderPtr() override { return &decoder; } |
211 | 212 |
212 Status status() const { return _status; } | 213 System *getSystemPtr() override { return system; } |
213 | 214 |
214 void setStatus(Status newStatus) { _status = newStatus; } | 215 TheISA::Kernel::Statistics * 216 getKernelStats() 217 { 218 return ThreadState::getKernelStats(); 219 } |
215 | 220 |
221 PortProxy &getPhysProxy() { return ThreadState::getPhysProxy(); } 222 FSTranslatingPortProxy & 223 getVirtProxy() 224 { 225 return ThreadState::getVirtProxy(); 226 } 227 228 void initMemProxies(ThreadContext *tc) { ThreadState::initMemProxies(tc); } 229 SETranslatingPortProxy & 230 getMemProxy() 231 { 232 return ThreadState::getMemProxy(); 233 } 234 235 Process *getProcessPtr() { return ThreadState::getProcessPtr(); } 236 void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); } 237 238 Status status() const override { return _status; } 239 240 void setStatus(Status newStatus) override { _status = newStatus; } 241 |
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216 /// Set the status to Active. | 242 /// Set the status to Active. |
217 void activate(); | 243 void activate() override; |
218 219 /// Set the status to Suspended. | 244 245 /// Set the status to Suspended. |
220 void suspend(); | 246 void suspend() override; |
221 222 /// Set the status to Halted. | 247 248 /// Set the status to Halted. |
223 void halt(); | 249 void halt() override; |
224 | 250 |
225 void copyArchRegs(ThreadContext *tc); | 251 EndQuiesceEvent * 252 getQuiesceEvent() override 253 { 254 return ThreadState::getQuiesceEvent(); 255 } |
226 | 256 |
227 void clearArchRegs() | 257 Tick 258 readLastActivate() override |
228 { | 259 { |
260 return ThreadState::readLastActivate(); 261 } 262 Tick 263 readLastSuspend() override 264 { 265 return ThreadState::readLastSuspend(); 266 } 267 268 void profileClear() override { ThreadState::profileClear(); } 269 void profileSample() override { ThreadState::profileSample(); } 270 271 void copyArchRegs(ThreadContext *tc) override; 272 273 void clearArchRegs() override 274 { |
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229 _pcState = 0; 230 memset(intRegs, 0, sizeof(intRegs)); 231 memset(floatRegs, 0, sizeof(floatRegs)); 232 for (int i = 0; i < TheISA::NumVecRegs; i++) { 233 vecRegs[i].zero(); 234 } 235 for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 236 vecPredRegs[i].reset(); 237 } 238#ifdef ISA_HAS_CC_REGS 239 memset(ccRegs, 0, sizeof(ccRegs)); 240#endif 241 isa->clear(); 242 } 243 244 // 245 // New accessors for new decoder. 246 // 247 RegVal | 275 _pcState = 0; 276 memset(intRegs, 0, sizeof(intRegs)); 277 memset(floatRegs, 0, sizeof(floatRegs)); 278 for (int i = 0; i < TheISA::NumVecRegs; i++) { 279 vecRegs[i].zero(); 280 } 281 for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 282 vecPredRegs[i].reset(); 283 } 284#ifdef ISA_HAS_CC_REGS 285 memset(ccRegs, 0, sizeof(ccRegs)); 286#endif 287 isa->clear(); 288 } 289 290 // 291 // New accessors for new decoder. 292 // 293 RegVal |
248 readIntReg(int reg_idx) | 294 readIntReg(RegIndex reg_idx) const override |
249 { 250 int flatIndex = isa->flattenIntIndex(reg_idx); 251 assert(flatIndex < TheISA::NumIntRegs); 252 uint64_t regVal(readIntRegFlat(flatIndex)); 253 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 254 reg_idx, flatIndex, regVal); 255 return regVal; 256 } 257 258 RegVal | 295 { 296 int flatIndex = isa->flattenIntIndex(reg_idx); 297 assert(flatIndex < TheISA::NumIntRegs); 298 uint64_t regVal(readIntRegFlat(flatIndex)); 299 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 300 reg_idx, flatIndex, regVal); 301 return regVal; 302 } 303 304 RegVal |
259 readFloatReg(int reg_idx) | 305 readFloatReg(RegIndex reg_idx) const override |
260 { 261 int flatIndex = isa->flattenFloatIndex(reg_idx); 262 assert(flatIndex < TheISA::NumFloatRegs); 263 RegVal regVal(readFloatRegFlat(flatIndex)); 264 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 265 reg_idx, flatIndex, regVal); 266 return regVal; 267 } 268 269 const VecRegContainer& | 306 { 307 int flatIndex = isa->flattenFloatIndex(reg_idx); 308 assert(flatIndex < TheISA::NumFloatRegs); 309 RegVal regVal(readFloatRegFlat(flatIndex)); 310 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 311 reg_idx, flatIndex, regVal); 312 return regVal; 313 } 314 315 const VecRegContainer& |
270 readVecReg(const RegId& reg) const | 316 readVecReg(const RegId& reg) const override |
271 { 272 int flatIndex = isa->flattenVecIndex(reg.index()); 273 assert(flatIndex < TheISA::NumVecRegs); 274 const VecRegContainer& regVal = readVecRegFlat(flatIndex); 275 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 276 reg.index(), flatIndex, regVal.print()); 277 return regVal; 278 } 279 280 VecRegContainer& | 317 { 318 int flatIndex = isa->flattenVecIndex(reg.index()); 319 assert(flatIndex < TheISA::NumVecRegs); 320 const VecRegContainer& regVal = readVecRegFlat(flatIndex); 321 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 322 reg.index(), flatIndex, regVal.print()); 323 return regVal; 324 } 325 326 VecRegContainer& |
281 getWritableVecReg(const RegId& reg) | 327 getWritableVecReg(const RegId& reg) override |
282 { 283 int flatIndex = isa->flattenVecIndex(reg.index()); 284 assert(flatIndex < TheISA::NumVecRegs); 285 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 286 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 287 reg.index(), flatIndex, regVal.print()); 288 return regVal; 289 } --- 10 unchanged lines hidden (view full) --- 300 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 301 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 302 reg.index(), flatIndex, reg.elemIndex(), regVal); 303 return regVal; 304 } 305 306 /** Reads source vector 8bit operand. */ 307 virtual ConstVecLane8 | 328 { 329 int flatIndex = isa->flattenVecIndex(reg.index()); 330 assert(flatIndex < TheISA::NumVecRegs); 331 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 332 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 333 reg.index(), flatIndex, regVal.print()); 334 return regVal; 335 } --- 10 unchanged lines hidden (view full) --- 346 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 347 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 348 reg.index(), flatIndex, reg.elemIndex(), regVal); 349 return regVal; 350 } 351 352 /** Reads source vector 8bit operand. */ 353 virtual ConstVecLane8 |
308 readVec8BitLaneReg(const RegId& reg) const 309 { return readVecLane<uint8_t>(reg); } | 354 readVec8BitLaneReg(const RegId ®) const override 355 { 356 return readVecLane<uint8_t>(reg); 357 } |
310 311 /** Reads source vector 16bit operand. */ 312 virtual ConstVecLane16 | 358 359 /** Reads source vector 16bit operand. */ 360 virtual ConstVecLane16 |
313 readVec16BitLaneReg(const RegId& reg) const 314 { return readVecLane<uint16_t>(reg); } | 361 readVec16BitLaneReg(const RegId ®) const override 362 { 363 return readVecLane<uint16_t>(reg); 364 } |
315 316 /** Reads source vector 32bit operand. */ 317 virtual ConstVecLane32 | 365 366 /** Reads source vector 32bit operand. */ 367 virtual ConstVecLane32 |
318 readVec32BitLaneReg(const RegId& reg) const 319 { return readVecLane<uint32_t>(reg); } | 368 readVec32BitLaneReg(const RegId ®) const override 369 { 370 return readVecLane<uint32_t>(reg); 371 } |
320 321 /** Reads source vector 64bit operand. */ 322 virtual ConstVecLane64 | 372 373 /** Reads source vector 64bit operand. */ 374 virtual ConstVecLane64 |
323 readVec64BitLaneReg(const RegId& reg) const 324 { return readVecLane<uint64_t>(reg); } | 375 readVec64BitLaneReg(const RegId ®) const override 376 { 377 return readVecLane<uint64_t>(reg); 378 } |
325 326 /** Write a lane of the destination vector register. */ 327 template <typename LD> | 379 380 /** Write a lane of the destination vector register. */ 381 template <typename LD> |
328 void setVecLaneT(const RegId& reg, const LD& val) | 382 void 383 setVecLaneT(const RegId ®, const LD &val) |
329 { 330 int flatIndex = isa->flattenVecIndex(reg.index()); 331 assert(flatIndex < TheISA::NumVecRegs); 332 setVecLaneFlat(flatIndex, reg.elemIndex(), val); 333 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 334 reg.index(), flatIndex, reg.elemIndex(), val); 335 } | 384 { 385 int flatIndex = isa->flattenVecIndex(reg.index()); 386 assert(flatIndex < TheISA::NumVecRegs); 387 setVecLaneFlat(flatIndex, reg.elemIndex(), val); 388 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 389 reg.index(), flatIndex, reg.elemIndex(), val); 390 } |
336 virtual void setVecLane(const RegId& reg, 337 const LaneData<LaneSize::Byte>& val) 338 { return setVecLaneT(reg, val); } 339 virtual void setVecLane(const RegId& reg, 340 const LaneData<LaneSize::TwoByte>& val) 341 { return setVecLaneT(reg, val); } 342 virtual void setVecLane(const RegId& reg, 343 const LaneData<LaneSize::FourByte>& val) 344 { return setVecLaneT(reg, val); } 345 virtual void setVecLane(const RegId& reg, 346 const LaneData<LaneSize::EightByte>& val) 347 { return setVecLaneT(reg, val); } | 391 virtual void 392 setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val) override 393 { 394 return setVecLaneT(reg, val); 395 } 396 virtual void 397 setVecLane(const RegId ®, 398 const LaneData<LaneSize::TwoByte> &val) override 399 { 400 return setVecLaneT(reg, val); 401 } 402 virtual void 403 setVecLane(const RegId ®, 404 const LaneData<LaneSize::FourByte> &val) override 405 { 406 return setVecLaneT(reg, val); 407 } 408 virtual void 409 setVecLane(const RegId ®, 410 const LaneData<LaneSize::EightByte> &val) override 411 { 412 return setVecLaneT(reg, val); 413 } |
348 /** @} */ 349 | 414 /** @} */ 415 |
350 const VecElem& readVecElem(const RegId& reg) const | 416 const VecElem & 417 readVecElem(const RegId ®) const override |
351 { 352 int flatIndex = isa->flattenVecElemIndex(reg.index()); 353 assert(flatIndex < TheISA::NumVecRegs); 354 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 355 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 356 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 357 return regVal; 358 } 359 | 418 { 419 int flatIndex = isa->flattenVecElemIndex(reg.index()); 420 assert(flatIndex < TheISA::NumVecRegs); 421 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 422 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 423 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 424 return regVal; 425 } 426 |
360 const VecPredRegContainer& 361 readVecPredReg(const RegId& reg) const | 427 const VecPredRegContainer & 428 readVecPredReg(const RegId ®) const override |
362 { 363 int flatIndex = isa->flattenVecPredIndex(reg.index()); 364 assert(flatIndex < TheISA::NumVecPredRegs); 365 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 366 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 367 reg.index(), flatIndex, regVal.print()); 368 return regVal; 369 } 370 | 429 { 430 int flatIndex = isa->flattenVecPredIndex(reg.index()); 431 assert(flatIndex < TheISA::NumVecPredRegs); 432 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 433 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 434 reg.index(), flatIndex, regVal.print()); 435 return regVal; 436 } 437 |
371 VecPredRegContainer& 372 getWritableVecPredReg(const RegId& reg) | 438 VecPredRegContainer & 439 getWritableVecPredReg(const RegId ®) override |
373 { 374 int flatIndex = isa->flattenVecPredIndex(reg.index()); 375 assert(flatIndex < TheISA::NumVecPredRegs); 376 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 377 DPRINTF(VecPredRegs, 378 "Reading predicate reg %d (%d) as %s for modify.\n", 379 reg.index(), flatIndex, regVal.print()); 380 return regVal; 381 } 382 383 RegVal | 440 { 441 int flatIndex = isa->flattenVecPredIndex(reg.index()); 442 assert(flatIndex < TheISA::NumVecPredRegs); 443 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 444 DPRINTF(VecPredRegs, 445 "Reading predicate reg %d (%d) as %s for modify.\n", 446 reg.index(), flatIndex, regVal.print()); 447 return regVal; 448 } 449 450 RegVal |
384 readCCReg(int reg_idx) | 451 readCCReg(RegIndex reg_idx) const override |
385 { 386#ifdef ISA_HAS_CC_REGS 387 int flatIndex = isa->flattenCCIndex(reg_idx); 388 assert(0 <= flatIndex); 389 assert(flatIndex < TheISA::NumCCRegs); 390 uint64_t regVal(readCCRegFlat(flatIndex)); 391 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 392 reg_idx, flatIndex, regVal); 393 return regVal; 394#else 395 panic("Tried to read a CC register."); 396 return 0; 397#endif 398 } 399 400 void | 452 { 453#ifdef ISA_HAS_CC_REGS 454 int flatIndex = isa->flattenCCIndex(reg_idx); 455 assert(0 <= flatIndex); 456 assert(flatIndex < TheISA::NumCCRegs); 457 uint64_t regVal(readCCRegFlat(flatIndex)); 458 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 459 reg_idx, flatIndex, regVal); 460 return regVal; 461#else 462 panic("Tried to read a CC register."); 463 return 0; 464#endif 465 } 466 467 void |
401 setIntReg(int reg_idx, RegVal val) | 468 setIntReg(RegIndex reg_idx, RegVal val) override |
402 { 403 int flatIndex = isa->flattenIntIndex(reg_idx); 404 assert(flatIndex < TheISA::NumIntRegs); 405 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 406 reg_idx, flatIndex, val); 407 setIntRegFlat(flatIndex, val); 408 } 409 410 void | 469 { 470 int flatIndex = isa->flattenIntIndex(reg_idx); 471 assert(flatIndex < TheISA::NumIntRegs); 472 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 473 reg_idx, flatIndex, val); 474 setIntRegFlat(flatIndex, val); 475 } 476 477 void |
411 setFloatReg(int reg_idx, RegVal val) | 478 setFloatReg(RegIndex reg_idx, RegVal val) override |
412 { 413 int flatIndex = isa->flattenFloatIndex(reg_idx); 414 assert(flatIndex < TheISA::NumFloatRegs); 415 // XXX: Fix array out of bounds compiler error for gem5.fast 416 // when checkercpu enabled 417 if (flatIndex < TheISA::NumFloatRegs) 418 setFloatRegFlat(flatIndex, val); 419 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 420 reg_idx, flatIndex, val); 421 } 422 423 void | 479 { 480 int flatIndex = isa->flattenFloatIndex(reg_idx); 481 assert(flatIndex < TheISA::NumFloatRegs); 482 // XXX: Fix array out of bounds compiler error for gem5.fast 483 // when checkercpu enabled 484 if (flatIndex < TheISA::NumFloatRegs) 485 setFloatRegFlat(flatIndex, val); 486 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 487 reg_idx, flatIndex, val); 488 } 489 490 void |
424 setVecReg(const RegId& reg, const VecRegContainer& val) | 491 setVecReg(const RegId ®, const VecRegContainer &val) override |
425 { 426 int flatIndex = isa->flattenVecIndex(reg.index()); 427 assert(flatIndex < TheISA::NumVecRegs); 428 setVecRegFlat(flatIndex, val); 429 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 430 reg.index(), flatIndex, val.print()); 431 } 432 433 void | 492 { 493 int flatIndex = isa->flattenVecIndex(reg.index()); 494 assert(flatIndex < TheISA::NumVecRegs); 495 setVecRegFlat(flatIndex, val); 496 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 497 reg.index(), flatIndex, val.print()); 498 } 499 500 void |
434 setVecElem(const RegId& reg, const VecElem& val) | 501 setVecElem(const RegId ®, const VecElem &val) override |
435 { 436 int flatIndex = isa->flattenVecElemIndex(reg.index()); 437 assert(flatIndex < TheISA::NumVecRegs); 438 setVecElemFlat(flatIndex, reg.elemIndex(), val); 439 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 440 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 441 } 442 443 void | 502 { 503 int flatIndex = isa->flattenVecElemIndex(reg.index()); 504 assert(flatIndex < TheISA::NumVecRegs); 505 setVecElemFlat(flatIndex, reg.elemIndex(), val); 506 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 507 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 508 } 509 510 void |
444 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) | 511 setVecPredReg(const RegId ®, const VecPredRegContainer &val) override |
445 { 446 int flatIndex = isa->flattenVecPredIndex(reg.index()); 447 assert(flatIndex < TheISA::NumVecPredRegs); 448 setVecPredRegFlat(flatIndex, val); 449 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 450 reg.index(), flatIndex, val.print()); 451 } 452 453 void | 512 { 513 int flatIndex = isa->flattenVecPredIndex(reg.index()); 514 assert(flatIndex < TheISA::NumVecPredRegs); 515 setVecPredRegFlat(flatIndex, val); 516 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 517 reg.index(), flatIndex, val.print()); 518 } 519 520 void |
454 setCCReg(int reg_idx, RegVal val) | 521 setCCReg(RegIndex reg_idx, RegVal val) override |
455 { 456#ifdef ISA_HAS_CC_REGS 457 int flatIndex = isa->flattenCCIndex(reg_idx); 458 assert(flatIndex < TheISA::NumCCRegs); 459 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 460 reg_idx, flatIndex, val); 461 setCCRegFlat(flatIndex, val); 462#else 463 panic("Tried to set a CC register."); 464#endif 465 } 466 | 522 { 523#ifdef ISA_HAS_CC_REGS 524 int flatIndex = isa->flattenCCIndex(reg_idx); 525 assert(flatIndex < TheISA::NumCCRegs); 526 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 527 reg_idx, flatIndex, val); 528 setCCRegFlat(flatIndex, val); 529#else 530 panic("Tried to set a CC register."); 531#endif 532 } 533 |
467 TheISA::PCState 468 pcState() 469 { 470 return _pcState; 471 } | 534 TheISA::PCState pcState() const override { return _pcState; } 535 void pcState(const TheISA::PCState &val) override { _pcState = val; } |
472 473 void | 536 537 void |
474 pcState(const TheISA::PCState &val) | 538 pcStateNoRecord(const TheISA::PCState &val) override |
475 { 476 _pcState = val; 477 } 478 | 539 { 540 _pcState = val; 541 } 542 |
479 void 480 pcStateNoRecord(const TheISA::PCState &val) 481 { 482 _pcState = val; 483 } | 543 Addr instAddr() const override { return _pcState.instAddr(); } 544 Addr nextInstAddr() const override { return _pcState.nextInstAddr(); } 545 MicroPC microPC() const override { return _pcState.microPC(); } 546 bool readPredicate() const { return predicate; } 547 void setPredicate(bool val) { predicate = val; } |
484 | 548 |
485 Addr 486 instAddr() | 549 RegVal 550 readMiscRegNoEffect(RegIndex misc_reg) const override |
487 { | 551 { |
488 return _pcState.instAddr(); | 552 return isa->readMiscRegNoEffect(misc_reg); |
489 } 490 | 553 } 554 |
491 Addr 492 nextInstAddr() | 555 RegVal 556 readMiscReg(RegIndex misc_reg) override |
493 { | 557 { |
494 return _pcState.nextInstAddr(); | 558 return isa->readMiscReg(misc_reg, this); |
495 } 496 497 void | 559 } 560 561 void |
498 setNPC(Addr val) | 562 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override |
499 { | 563 { |
500 _pcState.setNPC(val); | 564 return isa->setMiscRegNoEffect(misc_reg, val); |
501 } 502 | 565 } 566 |
503 MicroPC 504 microPC() | 567 void 568 setMiscReg(RegIndex misc_reg, RegVal val) override |
505 { | 569 { |
506 return _pcState.microPC(); | 570 return isa->setMiscReg(misc_reg, val, this); |
507 } 508 | 571 } 572 |
509 bool readPredicate() | 573 RegId 574 flattenRegId(const RegId& regId) const override |
510 { | 575 { |
511 return predicate; | 576 return isa->flattenRegId(regId); |
512 } 513 | 577 } 578 |
514 void setPredicate(bool val) 515 { 516 predicate = val; 517 } | 579 unsigned readStCondFailures() const override { return storeCondFailures; } |
518 | 580 |
519 RegVal 520 readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const | 581 void 582 setStCondFailures(unsigned sc_failures) override |
521 { | 583 { |
522 return isa->readMiscRegNoEffect(misc_reg); | 584 storeCondFailures = sc_failures; |
523 } 524 | 585 } 586 |
525 RegVal 526 readMiscReg(int misc_reg, ThreadID tid=0) | 587 Counter 588 readFuncExeInst() const override |
527 { | 589 { |
528 return isa->readMiscReg(misc_reg, tc); | 590 return ThreadState::readFuncExeInst(); |
529 } 530 531 void | 591 } 592 593 void |
532 setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0) | 594 syscall(int64_t callnum, Fault *fault) override |
533 { | 595 { |
534 return isa->setMiscRegNoEffect(misc_reg, val); | 596 process->syscall(callnum, this, fault); |
535 } 536 | 597 } 598 |
599 RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; } |
|
537 void | 600 void |
538 setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0) | 601 setIntRegFlat(RegIndex idx, RegVal val) override |
539 { | 602 { |
540 return isa->setMiscReg(misc_reg, val, tc); | 603 intRegs[idx] = val; |
541 } 542 | 604 } 605 |
543 RegId 544 flattenRegId(const RegId& regId) const | 606 RegVal 607 readFloatRegFlat(RegIndex idx) const override |
545 { | 608 { |
546 return isa->flattenRegId(regId); | 609 return floatRegs[idx]; |
547 } | 610 } |
548 549 unsigned readStCondFailures() { return storeCondFailures; } 550 551 void setStCondFailures(unsigned sc_failures) 552 { storeCondFailures = sc_failures; } 553 | |
554 void | 611 void |
555 syscall(int64_t callnum, Fault *fault) | 612 setFloatRegFlat(RegIndex idx, RegVal val) override |
556 { | 613 { |
557 process->syscall(callnum, tc, fault); | 614 floatRegs[idx] = val; |
558 } 559 | 615 } 616 |
560 RegVal readIntRegFlat(int idx) { return intRegs[idx]; } 561 void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } 562 563 RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; } 564 void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; } 565 | |
566 const VecRegContainer & | 617 const VecRegContainer & |
567 readVecRegFlat(const RegIndex& reg) const | 618 readVecRegFlat(RegIndex reg) const override |
568 { 569 return vecRegs[reg]; 570 } 571 572 VecRegContainer & | 619 { 620 return vecRegs[reg]; 621 } 622 623 VecRegContainer & |
573 getWritableVecRegFlat(const RegIndex& reg) | 624 getWritableVecRegFlat(RegIndex reg) override |
574 { 575 return vecRegs[reg]; 576 } 577 578 void | 625 { 626 return vecRegs[reg]; 627 } 628 629 void |
579 setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) | 630 setVecRegFlat(RegIndex reg, const VecRegContainer &val) override |
580 { 581 vecRegs[reg] = val; 582 } 583 584 template <typename T> 585 VecLaneT<T, true> | 631 { 632 vecRegs[reg] = val; 633 } 634 635 template <typename T> 636 VecLaneT<T, true> |
586 readVecLaneFlat(const RegIndex& reg, int lId) const | 637 readVecLaneFlat(RegIndex reg, int lId) const |
587 { 588 return vecRegs[reg].laneView<T>(lId); 589 } 590 591 template <typename LD> 592 void | 638 { 639 return vecRegs[reg].laneView<T>(lId); 640 } 641 642 template <typename LD> 643 void |
593 setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) | 644 setVecLaneFlat(RegIndex reg, int lId, const LD &val) |
594 { 595 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 596 } 597 598 const VecElem & | 645 { 646 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 647 } 648 649 const VecElem & |
599 readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const | 650 readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override |
600 { 601 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 602 } 603 604 void | 651 { 652 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 653 } 654 655 void |
605 setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 606 const VecElem val) | 656 setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex, 657 const VecElem &val) override |
607 { 608 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 609 } 610 | 658 { 659 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 660 } 661 |
611 const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const | 662 const VecPredRegContainer & 663 readVecPredRegFlat(RegIndex reg) const override |
612 { 613 return vecPredRegs[reg]; 614 } 615 | 664 { 665 return vecPredRegs[reg]; 666 } 667 |
616 VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg) | 668 VecPredRegContainer & 669 getWritableVecPredRegFlat(RegIndex reg) override |
617 { 618 return vecPredRegs[reg]; 619 } 620 | 670 { 671 return vecPredRegs[reg]; 672 } 673 |
621 void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val) | 674 void 675 setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override |
622 { 623 vecPredRegs[reg] = val; 624 } 625 626#ifdef ISA_HAS_CC_REGS | 676 { 677 vecPredRegs[reg] = val; 678 } 679 680#ifdef ISA_HAS_CC_REGS |
627 RegVal readCCRegFlat(int idx) { return ccRegs[idx]; } 628 void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; } | 681 RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; } 682 void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; } |
629#else | 683#else |
630 RegVal readCCRegFlat(int idx) 631 { panic("readCCRegFlat w/no CC regs!\n"); } | 684 RegVal 685 readCCRegFlat(RegIndex idx) const override 686 { 687 panic("readCCRegFlat w/no CC regs!\n"); 688 } |
632 | 689 |
633 void setCCRegFlat(int idx, RegVal val) 634 { panic("setCCRegFlat w/no CC regs!\n"); } | 690 void 691 setCCRegFlat(RegIndex idx, RegVal val) override 692 { 693 panic("setCCRegFlat w/no CC regs!\n"); 694 } |
635#endif 636}; 637 638 639#endif // __CPU_CPU_EXEC_CONTEXT_HH__ | 695#endif 696}; 697 698 699#endif // __CPU_CPU_EXEC_CONTEXT_HH__ |