simple_thread.hh (13611:c8b7847b4171) simple_thread.hh (13622:ba31c2a23eca)
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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95 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
96 * examples.
97 */
98
99class SimpleThread : public ThreadState
100{
101 protected:
102 typedef TheISA::MachInst MachInst;
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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95 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
96 * examples.
97 */
98
99class SimpleThread : public ThreadState
100{
101 protected:
102 typedef TheISA::MachInst MachInst;
103 typedef TheISA::CCReg CCReg;
104 using VecRegContainer = TheISA::VecRegContainer;
105 using VecElem = TheISA::VecElem;
106 using VecPredRegContainer = TheISA::VecPredRegContainer;
107 public:
108 typedef ThreadContext::Status Status;
109
110 protected:
111 RegVal floatRegs[TheISA::NumFloatRegs];
112 RegVal intRegs[TheISA::NumIntRegs];
113 VecRegContainer vecRegs[TheISA::NumVecRegs];
114 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
115#ifdef ISA_HAS_CC_REGS
103 using VecRegContainer = TheISA::VecRegContainer;
104 using VecElem = TheISA::VecElem;
105 using VecPredRegContainer = TheISA::VecPredRegContainer;
106 public:
107 typedef ThreadContext::Status Status;
108
109 protected:
110 RegVal floatRegs[TheISA::NumFloatRegs];
111 RegVal intRegs[TheISA::NumIntRegs];
112 VecRegContainer vecRegs[TheISA::NumVecRegs];
113 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
114#ifdef ISA_HAS_CC_REGS
116 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
115 RegVal ccRegs[TheISA::NumCCRegs];
117#endif
118 TheISA::ISA *const isa; // one "instance" of the current ISA.
119
120 TheISA::PCState _pcState;
121
122 /** Did this instruction execute or is it predicated false */
123 bool predicate;
124

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374 assert(flatIndex < TheISA::NumVecPredRegs);
375 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex);
376 DPRINTF(VecPredRegs,
377 "Reading predicate reg %d (%d) as %s for modify.\n",
378 reg.index(), flatIndex, regVal.print());
379 return regVal;
380 }
381
116#endif
117 TheISA::ISA *const isa; // one "instance" of the current ISA.
118
119 TheISA::PCState _pcState;
120
121 /** Did this instruction execute or is it predicated false */
122 bool predicate;
123

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373 assert(flatIndex < TheISA::NumVecPredRegs);
374 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex);
375 DPRINTF(VecPredRegs,
376 "Reading predicate reg %d (%d) as %s for modify.\n",
377 reg.index(), flatIndex, regVal.print());
378 return regVal;
379 }
380
382 CCReg readCCReg(int reg_idx)
381 RegVal
382 readCCReg(int reg_idx)
383 {
384#ifdef ISA_HAS_CC_REGS
385 int flatIndex = isa->flattenCCIndex(reg_idx);
386 assert(0 <= flatIndex);
387 assert(flatIndex < TheISA::NumCCRegs);
388 uint64_t regVal(readCCRegFlat(flatIndex));
389 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
390 reg_idx, flatIndex, regVal);

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444 int flatIndex = isa->flattenVecPredIndex(reg.index());
445 assert(flatIndex < TheISA::NumVecPredRegs);
446 setVecPredRegFlat(flatIndex, val);
447 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
448 reg.index(), flatIndex, val.print());
449 }
450
451 void
383 {
384#ifdef ISA_HAS_CC_REGS
385 int flatIndex = isa->flattenCCIndex(reg_idx);
386 assert(0 <= flatIndex);
387 assert(flatIndex < TheISA::NumCCRegs);
388 uint64_t regVal(readCCRegFlat(flatIndex));
389 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
390 reg_idx, flatIndex, regVal);

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444 int flatIndex = isa->flattenVecPredIndex(reg.index());
445 assert(flatIndex < TheISA::NumVecPredRegs);
446 setVecPredRegFlat(flatIndex, val);
447 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
448 reg.index(), flatIndex, val.print());
449 }
450
451 void
452 setCCReg(int reg_idx, CCReg val)
452 setCCReg(int reg_idx, RegVal val)
453 {
454#ifdef ISA_HAS_CC_REGS
455 int flatIndex = isa->flattenCCIndex(reg_idx);
456 assert(flatIndex < TheISA::NumCCRegs);
457 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
458 reg_idx, flatIndex, val);
459 setCCRegFlat(flatIndex, val);
460#else

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617 }
618
619 void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val)
620 {
621 vecPredRegs[reg] = val;
622 }
623
624#ifdef ISA_HAS_CC_REGS
453 {
454#ifdef ISA_HAS_CC_REGS
455 int flatIndex = isa->flattenCCIndex(reg_idx);
456 assert(flatIndex < TheISA::NumCCRegs);
457 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
458 reg_idx, flatIndex, val);
459 setCCRegFlat(flatIndex, val);
460#else

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617 }
618
619 void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val)
620 {
621 vecPredRegs[reg] = val;
622 }
623
624#ifdef ISA_HAS_CC_REGS
625 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
626 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
625 RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
626 void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
627#else
627#else
628 CCReg readCCRegFlat(int idx)
628 RegVal readCCRegFlat(int idx)
629 { panic("readCCRegFlat w/no CC regs!\n"); }
630
629 { panic("readCCRegFlat w/no CC regs!\n"); }
630
631 void setCCRegFlat(int idx, CCReg val)
631 void setCCRegFlat(int idx, RegVal val)
632 { panic("setCCRegFlat w/no CC regs!\n"); }
633#endif
634};
635
636
637#endif // __CPU_CPU_EXEC_CONTEXT_HH__
632 { panic("setCCRegFlat w/no CC regs!\n"); }
633#endif
634};
635
636
637#endif // __CPU_CPU_EXEC_CONTEXT_HH__