simple_thread.hh (13582:989577bf6abc) | simple_thread.hh (13610:5d5404ac6288) |
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1/* | 1/* |
2 * Copyright (c) 2011-2012, 2016 ARM Limited | 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 42 unchanged lines hidden (view full) --- 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" | 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 42 unchanged lines hidden (view full) --- 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" |
61#include "debug/VecPredRegs.hh" |
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61#include "debug/VecRegs.hh" 62#include "mem/page_table.hh" 63#include "mem/request.hh" 64#include "sim/byteswap.hh" 65#include "sim/eventq.hh" 66#include "sim/process.hh" 67#include "sim/serialize.hh" 68#include "sim/system.hh" --- 28 unchanged lines hidden (view full) --- 97 98class SimpleThread : public ThreadState 99{ 100 protected: 101 typedef TheISA::MachInst MachInst; 102 typedef TheISA::CCReg CCReg; 103 using VecRegContainer = TheISA::VecRegContainer; 104 using VecElem = TheISA::VecElem; | 62#include "debug/VecRegs.hh" 63#include "mem/page_table.hh" 64#include "mem/request.hh" 65#include "sim/byteswap.hh" 66#include "sim/eventq.hh" 67#include "sim/process.hh" 68#include "sim/serialize.hh" 69#include "sim/system.hh" --- 28 unchanged lines hidden (view full) --- 98 99class SimpleThread : public ThreadState 100{ 101 protected: 102 typedef TheISA::MachInst MachInst; 103 typedef TheISA::CCReg CCReg; 104 using VecRegContainer = TheISA::VecRegContainer; 105 using VecElem = TheISA::VecElem; |
106 using VecPredRegContainer = TheISA::VecPredRegContainer; |
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105 public: 106 typedef ThreadContext::Status Status; 107 108 protected: 109 RegVal floatRegs[TheISA::NumFloatRegs]; 110 RegVal intRegs[TheISA::NumIntRegs]; 111 VecRegContainer vecRegs[TheISA::NumVecRegs]; | 107 public: 108 typedef ThreadContext::Status Status; 109 110 protected: 111 RegVal floatRegs[TheISA::NumFloatRegs]; 112 RegVal intRegs[TheISA::NumIntRegs]; 113 VecRegContainer vecRegs[TheISA::NumVecRegs]; |
114 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs]; |
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112#ifdef ISA_HAS_CC_REGS 113 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 114#endif 115 TheISA::ISA *const isa; // one "instance" of the current ISA. 116 117 TheISA::PCState _pcState; 118 119 /** Did this instruction execute or is it predicated false */ --- 103 unchanged lines hidden (view full) --- 223 void clearArchRegs() 224 { 225 _pcState = 0; 226 memset(intRegs, 0, sizeof(intRegs)); 227 memset(floatRegs, 0, sizeof(floatRegs)); 228 for (int i = 0; i < TheISA::NumVecRegs; i++) { 229 vecRegs[i].zero(); 230 } | 115#ifdef ISA_HAS_CC_REGS 116 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 117#endif 118 TheISA::ISA *const isa; // one "instance" of the current ISA. 119 120 TheISA::PCState _pcState; 121 122 /** Did this instruction execute or is it predicated false */ --- 103 unchanged lines hidden (view full) --- 226 void clearArchRegs() 227 { 228 _pcState = 0; 229 memset(intRegs, 0, sizeof(intRegs)); 230 memset(floatRegs, 0, sizeof(floatRegs)); 231 for (int i = 0; i < TheISA::NumVecRegs; i++) { 232 vecRegs[i].zero(); 233 } |
234 for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 235 vecPredRegs[i].reset(); 236 } |
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231#ifdef ISA_HAS_CC_REGS 232 memset(ccRegs, 0, sizeof(ccRegs)); 233#endif 234 isa->clear(); 235 } 236 237 // 238 // New accessors for new decoder. --- 22 unchanged lines hidden (view full) --- 261 262 const VecRegContainer& 263 readVecReg(const RegId& reg) const 264 { 265 int flatIndex = isa->flattenVecIndex(reg.index()); 266 assert(flatIndex < TheISA::NumVecRegs); 267 const VecRegContainer& regVal = readVecRegFlat(flatIndex); 268 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", | 237#ifdef ISA_HAS_CC_REGS 238 memset(ccRegs, 0, sizeof(ccRegs)); 239#endif 240 isa->clear(); 241 } 242 243 // 244 // New accessors for new decoder. --- 22 unchanged lines hidden (view full) --- 267 268 const VecRegContainer& 269 readVecReg(const RegId& reg) const 270 { 271 int flatIndex = isa->flattenVecIndex(reg.index()); 272 assert(flatIndex < TheISA::NumVecRegs); 273 const VecRegContainer& regVal = readVecRegFlat(flatIndex); 274 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", |
269 reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); | 275 reg.index(), flatIndex, regVal.print()); |
270 return regVal; 271 } 272 273 VecRegContainer& 274 getWritableVecReg(const RegId& reg) 275 { 276 int flatIndex = isa->flattenVecIndex(reg.index()); 277 assert(flatIndex < TheISA::NumVecRegs); 278 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 279 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", | 276 return regVal; 277 } 278 279 VecRegContainer& 280 getWritableVecReg(const RegId& reg) 281 { 282 int flatIndex = isa->flattenVecIndex(reg.index()); 283 assert(flatIndex < TheISA::NumVecRegs); 284 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 285 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", |
280 reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); | 286 reg.index(), flatIndex, regVal.print()); |
281 return regVal; 282 } 283 284 /** Vector Register Lane Interfaces. */ 285 /** @{ */ 286 /** Reads source vector <T> operand. */ 287 template <typename T> 288 VecLaneT<T, true> --- 56 unchanged lines hidden (view full) --- 345 int flatIndex = isa->flattenVecElemIndex(reg.index()); 346 assert(flatIndex < TheISA::NumVecRegs); 347 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 348 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 349 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 350 return regVal; 351 } 352 | 287 return regVal; 288 } 289 290 /** Vector Register Lane Interfaces. */ 291 /** @{ */ 292 /** Reads source vector <T> operand. */ 293 template <typename T> 294 VecLaneT<T, true> --- 56 unchanged lines hidden (view full) --- 351 int flatIndex = isa->flattenVecElemIndex(reg.index()); 352 assert(flatIndex < TheISA::NumVecRegs); 353 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 354 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 355 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 356 return regVal; 357 } 358 |
359 const VecPredRegContainer& 360 readVecPredReg(const RegId& reg) const 361 { 362 int flatIndex = isa->flattenVecPredIndex(reg.index()); 363 assert(flatIndex < TheISA::NumVecPredRegs); 364 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 365 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 366 reg.index(), flatIndex, regVal.print()); 367 return regVal; 368 } |
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353 | 369 |
370 VecPredRegContainer& 371 getWritableVecPredReg(const RegId& reg) 372 { 373 int flatIndex = isa->flattenVecPredIndex(reg.index()); 374 assert(flatIndex < TheISA::NumVecPredRegs); 375 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 376 DPRINTF(VecPredRegs, 377 "Reading predicate reg %d (%d) as %s for modify.\n", 378 reg.index(), flatIndex, regVal.print()); 379 return regVal; 380 } 381 |
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354 CCReg readCCReg(int reg_idx) 355 { 356#ifdef ISA_HAS_CC_REGS 357 int flatIndex = isa->flattenCCIndex(reg_idx); 358 assert(0 <= flatIndex); 359 assert(flatIndex < TheISA::NumCCRegs); 360 uint64_t regVal(readCCRegFlat(flatIndex)); 361 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", --- 44 unchanged lines hidden (view full) --- 406 int flatIndex = isa->flattenVecElemIndex(reg.index()); 407 assert(flatIndex < TheISA::NumVecRegs); 408 setVecElemFlat(flatIndex, reg.elemIndex(), val); 409 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 410 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 411 } 412 413 void | 382 CCReg readCCReg(int reg_idx) 383 { 384#ifdef ISA_HAS_CC_REGS 385 int flatIndex = isa->flattenCCIndex(reg_idx); 386 assert(0 <= flatIndex); 387 assert(flatIndex < TheISA::NumCCRegs); 388 uint64_t regVal(readCCRegFlat(flatIndex)); 389 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", --- 44 unchanged lines hidden (view full) --- 434 int flatIndex = isa->flattenVecElemIndex(reg.index()); 435 assert(flatIndex < TheISA::NumVecRegs); 436 setVecElemFlat(flatIndex, reg.elemIndex(), val); 437 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 438 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 439 } 440 441 void |
442 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 443 { 444 int flatIndex = isa->flattenVecPredIndex(reg.index()); 445 assert(flatIndex < TheISA::NumVecPredRegs); 446 setVecPredRegFlat(flatIndex, val); 447 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 448 reg.index(), flatIndex, val.print()); 449 } 450 451 void |
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414 setCCReg(int reg_idx, CCReg val) 415 { 416#ifdef ISA_HAS_CC_REGS 417 int flatIndex = isa->flattenCCIndex(reg_idx); 418 assert(flatIndex < TheISA::NumCCRegs); 419 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 420 reg_idx, flatIndex, val); 421 setCCRegFlat(flatIndex, val); --- 141 unchanged lines hidden (view full) --- 563 564 void 565 setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 566 const VecElem val) 567 { 568 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 569 } 570 | 452 setCCReg(int reg_idx, CCReg val) 453 { 454#ifdef ISA_HAS_CC_REGS 455 int flatIndex = isa->flattenCCIndex(reg_idx); 456 assert(flatIndex < TheISA::NumCCRegs); 457 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 458 reg_idx, flatIndex, val); 459 setCCRegFlat(flatIndex, val); --- 141 unchanged lines hidden (view full) --- 601 602 void 603 setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 604 const VecElem val) 605 { 606 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 607 } 608 |
609 const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const 610 { 611 return vecPredRegs[reg]; 612 } 613 614 VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg) 615 { 616 return vecPredRegs[reg]; 617 } 618 619 void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val) 620 { 621 vecPredRegs[reg] = val; 622 } 623 |
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571#ifdef ISA_HAS_CC_REGS 572 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 573 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 574#else 575 CCReg readCCRegFlat(int idx) 576 { panic("readCCRegFlat w/no CC regs!\n"); } 577 578 void setCCRegFlat(int idx, CCReg val) 579 { panic("setCCRegFlat w/no CC regs!\n"); } 580#endif 581}; 582 583 584#endif // __CPU_CPU_EXEC_CONTEXT_HH__ | 624#ifdef ISA_HAS_CC_REGS 625 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 626 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 627#else 628 CCReg readCCRegFlat(int idx) 629 { panic("readCCRegFlat w/no CC regs!\n"); } 630 631 void setCCRegFlat(int idx, CCReg val) 632 { panic("setCCRegFlat w/no CC regs!\n"); } 633#endif 634}; 635 636 637#endif // __CPU_CPU_EXEC_CONTEXT_HH__ |