simple_thread.hh (13501:ce73744918e7) | simple_thread.hh (13557:fc33e6048b25) |
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1/* 2 * Copyright (c) 2011-2012, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 85 unchanged lines hidden (view full) --- 94 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 95 * examples. 96 */ 97 98class SimpleThread : public ThreadState 99{ 100 protected: 101 typedef TheISA::MachInst MachInst; | 1/* 2 * Copyright (c) 2011-2012, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 85 unchanged lines hidden (view full) --- 94 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 95 * examples. 96 */ 97 98class SimpleThread : public ThreadState 99{ 100 protected: 101 typedef TheISA::MachInst MachInst; |
102 typedef TheISA::MiscReg MiscReg; 103 typedef TheISA::FloatReg FloatReg; 104 typedef TheISA::FloatRegBits FloatRegBits; | |
105 typedef TheISA::CCReg CCReg; 106 using VecRegContainer = TheISA::VecRegContainer; 107 using VecElem = TheISA::VecElem; 108 public: 109 typedef ThreadContext::Status Status; 110 111 protected: | 102 typedef TheISA::CCReg CCReg; 103 using VecRegContainer = TheISA::VecRegContainer; 104 using VecElem = TheISA::VecElem; 105 public: 106 typedef ThreadContext::Status Status; 107 108 protected: |
112 FloatRegBits floatRegs[TheISA::NumFloatRegs]; 113 TheISA::IntReg intRegs[TheISA::NumIntRegs]; | 109 RegVal floatRegs[TheISA::NumFloatRegs]; 110 RegVal intRegs[TheISA::NumIntRegs]; |
114 VecRegContainer vecRegs[TheISA::NumVecRegs]; 115#ifdef ISA_HAS_CC_REGS 116 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 117#endif 118 TheISA::ISA *const isa; // one "instance" of the current ISA. 119 120 TheISA::PCState _pcState; 121 --- 113 unchanged lines hidden (view full) --- 235 memset(ccRegs, 0, sizeof(ccRegs)); 236#endif 237 isa->clear(); 238 } 239 240 // 241 // New accessors for new decoder. 242 // | 111 VecRegContainer vecRegs[TheISA::NumVecRegs]; 112#ifdef ISA_HAS_CC_REGS 113 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 114#endif 115 TheISA::ISA *const isa; // one "instance" of the current ISA. 116 117 TheISA::PCState _pcState; 118 --- 113 unchanged lines hidden (view full) --- 232 memset(ccRegs, 0, sizeof(ccRegs)); 233#endif 234 isa->clear(); 235 } 236 237 // 238 // New accessors for new decoder. 239 // |
243 uint64_t readIntReg(int reg_idx) | 240 RegVal 241 readIntReg(int reg_idx) |
244 { 245 int flatIndex = isa->flattenIntIndex(reg_idx); 246 assert(flatIndex < TheISA::NumIntRegs); 247 uint64_t regVal(readIntRegFlat(flatIndex)); 248 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 249 reg_idx, flatIndex, regVal); 250 return regVal; 251 } 252 | 242 { 243 int flatIndex = isa->flattenIntIndex(reg_idx); 244 assert(flatIndex < TheISA::NumIntRegs); 245 uint64_t regVal(readIntRegFlat(flatIndex)); 246 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 247 reg_idx, flatIndex, regVal); 248 return regVal; 249 } 250 |
253 FloatRegBits readFloatRegBits(int reg_idx) | 251 RegVal 252 readFloatRegBits(int reg_idx) |
254 { 255 int flatIndex = isa->flattenFloatIndex(reg_idx); 256 assert(flatIndex < TheISA::NumFloatRegs); | 253 { 254 int flatIndex = isa->flattenFloatIndex(reg_idx); 255 assert(flatIndex < TheISA::NumFloatRegs); |
257 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); | 256 RegVal regVal(readFloatRegBitsFlat(flatIndex)); |
258 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 259 reg_idx, flatIndex, regVal); 260 return regVal; 261 } 262 263 const VecRegContainer& 264 readVecReg(const RegId& reg) const 265 { --- 97 unchanged lines hidden (view full) --- 363 reg_idx, flatIndex, regVal); 364 return regVal; 365#else 366 panic("Tried to read a CC register."); 367 return 0; 368#endif 369 } 370 | 257 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 258 reg_idx, flatIndex, regVal); 259 return regVal; 260 } 261 262 const VecRegContainer& 263 readVecReg(const RegId& reg) const 264 { --- 97 unchanged lines hidden (view full) --- 362 reg_idx, flatIndex, regVal); 363 return regVal; 364#else 365 panic("Tried to read a CC register."); 366 return 0; 367#endif 368 } 369 |
371 void setIntReg(int reg_idx, uint64_t val) | 370 void 371 setIntReg(int reg_idx, RegVal val) |
372 { 373 int flatIndex = isa->flattenIntIndex(reg_idx); 374 assert(flatIndex < TheISA::NumIntRegs); 375 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 376 reg_idx, flatIndex, val); 377 setIntRegFlat(flatIndex, val); 378 } 379 | 372 { 373 int flatIndex = isa->flattenIntIndex(reg_idx); 374 assert(flatIndex < TheISA::NumIntRegs); 375 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 376 reg_idx, flatIndex, val); 377 setIntRegFlat(flatIndex, val); 378 } 379 |
380 void setFloatRegBits(int reg_idx, FloatRegBits val) | 380 void 381 setFloatRegBits(int reg_idx, RegVal val) |
381 { 382 int flatIndex = isa->flattenFloatIndex(reg_idx); 383 assert(flatIndex < TheISA::NumFloatRegs); 384 // XXX: Fix array out of bounds compiler error for gem5.fast 385 // when checkercpu enabled 386 if (flatIndex < TheISA::NumFloatRegs) 387 setFloatRegBitsFlat(flatIndex, val); 388 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 389 reg_idx, flatIndex, val); 390 } 391 | 382 { 383 int flatIndex = isa->flattenFloatIndex(reg_idx); 384 assert(flatIndex < TheISA::NumFloatRegs); 385 // XXX: Fix array out of bounds compiler error for gem5.fast 386 // when checkercpu enabled 387 if (flatIndex < TheISA::NumFloatRegs) 388 setFloatRegBitsFlat(flatIndex, val); 389 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 390 reg_idx, flatIndex, val); 391 } 392 |
392 void setVecReg(const RegId& reg, const VecRegContainer& val) | 393 void 394 setVecReg(const RegId& reg, const VecRegContainer& val) |
393 { 394 int flatIndex = isa->flattenVecIndex(reg.index()); 395 assert(flatIndex < TheISA::NumVecRegs); 396 setVecRegFlat(flatIndex, val); 397 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 398 reg.index(), flatIndex, val.print()); 399 } 400 | 395 { 396 int flatIndex = isa->flattenVecIndex(reg.index()); 397 assert(flatIndex < TheISA::NumVecRegs); 398 setVecRegFlat(flatIndex, val); 399 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 400 reg.index(), flatIndex, val.print()); 401 } 402 |
401 void setVecElem(const RegId& reg, const VecElem& val) | 403 void 404 setVecElem(const RegId& reg, const VecElem& val) |
402 { 403 int flatIndex = isa->flattenVecElemIndex(reg.index()); 404 assert(flatIndex < TheISA::NumVecRegs); 405 setVecElemFlat(flatIndex, reg.elemIndex(), val); 406 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 407 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 408 } 409 | 405 { 406 int flatIndex = isa->flattenVecElemIndex(reg.index()); 407 assert(flatIndex < TheISA::NumVecRegs); 408 setVecElemFlat(flatIndex, reg.elemIndex(), val); 409 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 410 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 411 } 412 |
410 void setCCReg(int reg_idx, CCReg val) | 413 void 414 setCCReg(int reg_idx, CCReg val) |
411 { 412#ifdef ISA_HAS_CC_REGS 413 int flatIndex = isa->flattenCCIndex(reg_idx); 414 assert(flatIndex < TheISA::NumCCRegs); 415 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 416 reg_idx, flatIndex, val); 417 setCCRegFlat(flatIndex, val); 418#else --- 48 unchanged lines hidden (view full) --- 467 return predicate; 468 } 469 470 void setPredicate(bool val) 471 { 472 predicate = val; 473 } 474 | 415 { 416#ifdef ISA_HAS_CC_REGS 417 int flatIndex = isa->flattenCCIndex(reg_idx); 418 assert(flatIndex < TheISA::NumCCRegs); 419 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 420 reg_idx, flatIndex, val); 421 setCCRegFlat(flatIndex, val); 422#else --- 48 unchanged lines hidden (view full) --- 471 return predicate; 472 } 473 474 void setPredicate(bool val) 475 { 476 predicate = val; 477 } 478 |
475 MiscReg 476 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const | 479 RegVal 480 readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const |
477 { 478 return isa->readMiscRegNoEffect(misc_reg); 479 } 480 | 481 { 482 return isa->readMiscRegNoEffect(misc_reg); 483 } 484 |
481 MiscReg 482 readMiscReg(int misc_reg, ThreadID tid = 0) | 485 RegVal 486 readMiscReg(int misc_reg, ThreadID tid=0) |
483 { 484 return isa->readMiscReg(misc_reg, tc); 485 } 486 487 void | 487 { 488 return isa->readMiscReg(misc_reg, tc); 489 } 490 491 void |
488 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) | 492 setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0) |
489 { 490 return isa->setMiscRegNoEffect(misc_reg, val); 491 } 492 493 void | 493 { 494 return isa->setMiscRegNoEffect(misc_reg, val); 495 } 496 497 void |
494 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) | 498 setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0) |
495 { 496 return isa->setMiscReg(misc_reg, val, tc); 497 } 498 499 RegId 500 flattenRegId(const RegId& regId) const 501 { 502 return isa->flattenRegId(regId); 503 } 504 505 unsigned readStCondFailures() { return storeCondFailures; } 506 507 void setStCondFailures(unsigned sc_failures) 508 { storeCondFailures = sc_failures; } 509 | 499 { 500 return isa->setMiscReg(misc_reg, val, tc); 501 } 502 503 RegId 504 flattenRegId(const RegId& regId) const 505 { 506 return isa->flattenRegId(regId); 507 } 508 509 unsigned readStCondFailures() { return storeCondFailures; } 510 511 void setStCondFailures(unsigned sc_failures) 512 { storeCondFailures = sc_failures; } 513 |
510 void syscall(int64_t callnum, Fault *fault) | 514 void 515 syscall(int64_t callnum, Fault *fault) |
511 { 512 process->syscall(callnum, tc, fault); 513 } 514 | 516 { 517 process->syscall(callnum, tc, fault); 518 } 519 |
515 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 516 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } | 520 RegVal readIntRegFlat(int idx) { return intRegs[idx]; } 521 void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } |
517 | 522 |
518 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } 519 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 520 floatRegs[idx] = val; 521 } | 523 RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } 524 void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } |
522 | 525 |
523 const VecRegContainer& readVecRegFlat(const RegIndex& reg) const | 526 const VecRegContainer & 527 readVecRegFlat(const RegIndex& reg) const |
524 { 525 return vecRegs[reg]; 526 } 527 | 528 { 529 return vecRegs[reg]; 530 } 531 |
528 VecRegContainer& getWritableVecRegFlat(const RegIndex& reg) | 532 VecRegContainer & 533 getWritableVecRegFlat(const RegIndex& reg) |
529 { 530 return vecRegs[reg]; 531 } 532 | 534 { 535 return vecRegs[reg]; 536 } 537 |
533 void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) | 538 void 539 setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) |
534 { 535 vecRegs[reg] = val; 536 } 537 538 template <typename T> | 540 { 541 vecRegs[reg] = val; 542 } 543 544 template <typename T> |
539 VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const | 545 VecLaneT 546 readVecLaneFlat(const RegIndex& reg, int lId) const |
540 { 541 return vecRegs[reg].laneView<T>(lId); 542 } 543 544 template <typename LD> | 547 { 548 return vecRegs[reg].laneView<T>(lId); 549 } 550 551 template <typename LD> |
545 void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) | 552 void 553 setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) |
546 { 547 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 548 } 549 | 554 { 555 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 556 } 557 |
550 const VecElem& readVecElemFlat(const RegIndex& reg, 551 const ElemIndex& elemIndex) const | 558 const VecElem & 559 readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const |
552 { 553 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 554 } 555 | 560 { 561 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 562 } 563 |
556 void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 557 const VecElem val) | 564 void 565 setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 566 const VecElem val) |
558 { 559 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 560 } 561 562#ifdef ISA_HAS_CC_REGS 563 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 564 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 565#else 566 CCReg readCCRegFlat(int idx) 567 { panic("readCCRegFlat w/no CC regs!\n"); } 568 569 void setCCRegFlat(int idx, CCReg val) 570 { panic("setCCRegFlat w/no CC regs!\n"); } 571#endif 572}; 573 574 575#endif // __CPU_CPU_EXEC_CONTEXT_HH__ | 567 { 568 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 569 } 570 571#ifdef ISA_HAS_CC_REGS 572 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 573 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 574#else 575 CCReg readCCRegFlat(int idx) 576 { panic("readCCRegFlat w/no CC regs!\n"); } 577 578 void setCCRegFlat(int idx, CCReg val) 579 { panic("setCCRegFlat w/no CC regs!\n"); } 580#endif 581}; 582 583 584#endif // __CPU_CPU_EXEC_CONTEXT_HH__ |